posted by Bryon Moyer
Silicon chips and the packages that house them have been steadily drawing closer to each other over the years. There are so many pins on individual dice now – and multiple dice are going into single packages. Optimizing which bumps from which dice go to which pins is a non-trivial project.
Part of the problem is that package design and die design have traditionally belonged to different departments using completely different tools that don’t talk to each other. That’s left engineers using Excel and such to try to visualize and plan pinouts.
The bulk of this isn’t changing – there is, as far as I know, no ubertool coming that includes both silicon and package design. But what can change is the means of planning the pinout – going to something more robust and efficient than Excel.
The same problem exists, by the way, with board design. Obviously, production board design is a process completely independent of die design; the die is designed once and then used on any number of boards. But optimizing board routing can also be challenging. Not to mention that doing some trial PCB layouts when planning the die isn’t a bad idea either.
Making this easier is the goal of Cadence’s new OrbitIO tool. It allows visualization and planning of signals. Because it couches its results as routing instructions and constraints, it’s a more dynamic way of planning; changes can be made with less work.
Once planned in OrbitIO, the results get pushed down into silicon design tools – Encounter or Virtuoso – in the form of a LEF/DEF die abstract file and to their multi-die package design tool, SiP-XL, via package data. They also get pushed to Allegro PCB on the board side, meaning that the die pinout’s effect can be evaluated all the way through to trial PCB layouts.
Image courtesy Cadence
In terms of evaluating what a “good” layout is, that’s partly visual, but the tool also provides lengths and number of routing layers as figures of merit. Note, however, that this analysis only goes as far as the pad ring on the die. Once planned, the effects of the pinout can be analyzed in the silicon design tool based on the data pushed to the tool by OrbitIO.
OrbitIO can be used most effectively if done prior to die floorplanning – it becomes an input to that floorplanning process. By handing data back and forth, the tools eliminate some of the tedious and error-prone steps that have to be taken with Excel and other hacks. Then pinout helps drive routing internally.
For multi-die packages, OrbitIO can work with dice in design, where pinouts can theoretically still be moved about, or with fixed dice – say, for a memory chip that’s being included in the package. The memory chip has no flexibility – it is what it is, so the tool needs to accommodate that.
If pinout is planned or changed after much of the die layout is in place, then the silicon tool can help evaluate the impact of the pinout on the die layout, and iteration is likely to find the best compromises.
You can find out more in Cadence’s announcement.
posted by Bryon Moyer
A while back Micralyne announced a MEMS reference process. There are a few of these running around: attempts to achieve – or at least grasp at – a standard process that can address a wide range of MEMS devices.
Most of Micralyne’s processes are confidential, per their customer relationships, in typical MEMS style. What they did here was to take a “neutral” improved version of what they do well and open it up. They’re not sure that customers will simply line up and use that process in high-volume production outright, but at the very least it’s a conversation starter and a way for them to show their capabilities without divulging secrets.
Micralyne’s strength is primarily optical MEMS: mirrors and comb drives and such. Those feature large in their process, but, in order to be a bit more general, they added some inertial devices, like a 2-axis (but not a 3-axis) accelerometer and a gyro, as well as some biomedical devices.
It’s a two-wafer process (plus handles); cavities are etched into the base wafer and the top wafer; the top wafer is inverted and fusion-bonded to the bottom wafer, after which the top-wafer handle is removed. From the top, release is performed and then metal is laid down. This metal step pertains in particularly to giving mirrors a nice reflective surface.
As a complete aside, in the discussion of their optical capabilities, there was repeated mention of “hitless” functionality with respect to the mirrors. I actually had a hard time finding out what this meant, and a conversation with Micralyne helped clarify. For any of you who are, like me, not steeped in optical, this is a way of changing optical routing in an optical switch without interfering with other channels.
It’s actually a pretty simple concept. Below I show a scenario with various fibers being routed to various other fibers via the gold mirrors. In particular, fiber 3 routes to fiber 1 (moving bottom to top). Let’s say we want to reroute that so that fiber 3 now routes to fiber 6. If we just move the mirror across, then the light stream from fiber three will interfere with all of the other receiving channels as it scans across (which I’ve tried to illustrate on the right, with the stars indicating interference as the beam moves; at the particular moment shown, it’s made it as far as target fiber 4 on its way to 6).
So the hitless idea is that you simple tilt the mirror in the orthogonal direction first so that it’s no longer targeting the receiving fibers. You can then sweep it across to the new target; the light is now moving under the other beams and doesn’t interfere. Once over in the new position, you then bring the beam back up to its normal working position and the connection is made (with no disturbance to the others).
You can find more info in their release and whitepapers.
posted by Bryon Moyer
Today’s note comes from the Department of Not What It Sounds Like. It’s about a company called Paper Battery, which doesn’t make batteries, and, what it does make isn’t made out of paper. The burdens of old names that stick…
What they do make is a supercapacitor. We’ve talked about supercaps before; there’s nothing revolutionary in concept. The story with PBC (much less confusing company name as an acronym… but don’t confuse it with PCB) is about their form factor: thin (0.3 mm) and flat. They can be, for instance, added as a “layer” over a battery to provide a combined battery/supercap “bundle” that has much more stable voltage.
Image courtesy Paper Battery Co.
The idea here is that such a flat component can be spread out in ways that use less space than explicit components that need their own plot of PCB. But the spatial efficiencies come with specific extra benefits, both electrical and thermal. As a layer or “wrap,” these supercaps can provide electromagnetic shielding; they can also act as head spreaders, helping wick away heat from hot spots that they might cover or underlie.
In the future, you could see multiple caps and voltages, paving the way for better DC/DC converters.
They say they have the technology sorted, but they’re optimizing for higher-volume manufacturing. In a few months they’ll make the decision to use either a contract manufacturer or to build a fab. If they roll their own, they say that it would be 12-16 months from now when they went live; they could get a contract guy going 3-4 months faster.
You can find more on their site.