posted by Jim Turley
One trillion. 1,000 billion. That's a big number. But that's how many semiconductor devices we're on track to produce and ship in 2017. This according to IC Insights and its latest market-research report. Obviously, that total includes just about everything that could conceivably be considered a semiconductor device, including digital chips, analog chips, opto sensors, and more. To reach that impressive sum, the company projects 10% growth in unit shipments this year, and another 11% growth next year. Good times.
posted by Bryon Moyer
Cavendish Kinetics recently made an announcement regarding their ongoing reliability testing for their MEMS-based antenna-tuning technology.
We’ve talked about this tuning concept before (albeit with a different name); the short version is that, with all of the different bands that cell phones need to access, it becomes difficult to optimize the antenna for all of them in the limited space available. So the idea is that you have a capacitor array switched by MEMS elements, and you can then change up your filter with each band to optimize accordingly.
We also looked in more depth at Cavendish Kinetics’ particular approach before, including a description of work they’ve done to limit the range of switching capacitor plates to keep them from over-traveling or slamming too hard against stops.
But, such assurances aside, the question phone makers have remains: how reliable are those MEMS elements? How many times can you switch them before they fail?
Well, according to Cavendish Kinetics, a lot. Like, 100 billion cycles and counting.
And who needs that many cycles? Well, no one, actually, according to them. But, hey, when you’re on a roll, might as well keep it going to put any lingering doubts to rest.
In my mind, I make some comparison to a gyroscope, which has to be in constant motion. Where there is literally a mechanical member moving (as opposed to techniques involving internal resonances), you can add up those movements pretty quickly. Billions aren’t hard to attain. Even if the frequency was a slow 1 kHz, you’d hit a hundred billion cycles in just over 3 years.
But here’s the difference: with the capacitor array, the elements move only when you change configuration. While in use in a particular configuration, the switches are static. If you changed configurations every second, then in three years you’d get roughly (just under) a billion switching events. Which means it would take running the system that aggressively for on the order of 300 years to get to a hundred billion cycles.
I’m thinking the battery would probably wear out first. (And it suggests that their test runs somewhat faster than 1 Hz…)
You can read more about this in their announcement.
posted by Bryon Moyer
Synopsys and Imec recently announced that they’d be collaborating on TCAD activities for the 5-nm node.
Yup. 5 nm. You can count ‘em on one hand.
We get to see lots of ideas on how things might happen in the future, but once you start defining a specific node, well, it’s time to get specific about what that node’s gonna look like. So I had a quick conversation with Imec’s Aaron Thean on what the notable changes would be at that node.
Because, unlike the old days, when each new node made things smaller, perhaps adding a new technique or tweak here and there to help with the shrinkage, these days it seems that, every couple nodes, something big has to change.
Like going from planar transistors to FinFETs. Or introducing double-patterning. And for all that work, it only buys you a couple nodes – you don’t get to reap the reward for the next 20 years. No time to relax; once you’ve gotten the latest major change completed, time to plan the next one.
While, presumably, each node has its share of evolutionary refinements from the prior node, I wanted to zero in on the big changes. One potentially big change that perhaps isn’t so big after all is EUV, but at 5 nm, they’ll still need double-patterning – even with EUV. So hopefully EUV won’t be new at that point – what a drag to have a new litho technology that can free us from double-patterning, only to have it delayed to the point where it also needs double-patterning. Doh!
So that’s not the big one. I hope. The big change is likely to be transistor orientation – again. He sees FinFETs living on down through the 7-nm node, but below that, routing challenges are finally going to be too great. At 7 nm, the channel will likely be nanowires instead of a fin, but it will still be horizontal. At the 5-nm node, they’re looking at flipping that nanowire up to make it vertical.
In other words, they’ll grow a “forest” of these – well, what I call “pins” – and create transistors out of them. I’ve referred to these in the past as “pinFETs.” Imec refers to them as “VFETs.”
By standing the channel up, you obviously reduce the transistor footprint dramatically. This frees up more routing room. But there’s also another big change: rather than the channel being contacted on the left and right, it’s now contacted on the top and bottom. That messes up the old convenient front-end and back-end distinction. Instead of all the interconnect going on top of the transistors, now the channel will reside between two layers of interconnect. So some of the interconnect will go down before the transistor is built.
They’ve done some trial layouts and have found a rather significant reduction in area by using such a transistor, as exemplified by the NAND gate below.
Image courtesy Imec
And when will all of this be coming to a fab near you? He sees 7-nm risk starts in the 2018 timeframe; 5 nm will lag that by only a couple years: 2020.
Oh, and in case you’re reserving time in your calendar, 3-4 nm risk starts are anticipated in the 2022-24 range.
I can hardly wait.