editor's blog
Subscribe Now

The Scribe and the Princess and the Pea

OK, perhaps “scribe line” is more accurate, but I do love a double entendre (even if not salacious). I had a discussion with KLA-Tencor at SPIE Litho recently regarding two new machines they’ve just announced. The first allows detection of defects through spectral analysis. The issue it faces is that it relies on test structures in the scribe line, which are facing two challenges: more of them are needed and there’s less space.

More test features are required both because of new structures like the FinFET and new processing steps, double-patterning in particular. But such structures have taken advantage of a generous scribe line area, dictated originally by the width or kerf of actual mechanical saws way back in the day. The cutting is done by laser now, so the kerf is no longer the issue. The scribe line is actually having a measurable impact on dice per wafer, so shrink it must.

The features that their SpectraShape 9000 analyzer looks for are periodic, and their spectra when illuminated by broadband light can be analyzed twelve ways from Sunday. Each of those features goes in a “box” that is currently 45 µm square. To accommodate the smaller scribe line, they’ve reduced the box size to 25 µm on a side (meaning they can almost put four of them where one of the old ones would have gone).

This has come with higher broadband light power, improved sensitivity, and higher throughput for more sampling.

Meanwhile, we’ve come to the point where the smallest (OK, maybe not smallest, but very small) particle – on the backside of the wafer – can push the upper surface out of the depth of field during exposure. Seriously. Total princess-and-pea situation. It gets worse because smaller particles tend to stick harder due to van der Waals forces. And yet such a particle may transfer to the chuck, sharing the donation with the next wafers to come through.

Rather than noticing the effect of such a particle and then going and figuring out where it is, they’ve created a new use model: inspect the backside.* Of each wafer, before it goes into a process. This prevents the particles from ever getting into the chamber – as long as it can be done quickly enough to keep the line moving.

They’ve boosted sensitivity on their BDR300 by 10x to allow for detection of half-micron defects at 100 wafers/hour. They also have a review capability, allowing inspection of defects down to 0.2 µm. It can be integrated into their CIRCL cluster.

You can find out more about these machines in their release.

 

 

*There’s so much potential for abusing this… especially when looking for defects like paddle marks… but this is a family newspaper. Oh, OK, who am I kidding…

Leave a Reply

featured blogs
Apr 24, 2024
Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified through our culture at Cadence. In the DEI@Cadence blog series, you'll find a community where employees share their perspectives and experiences. By providing a glimpse of their personal...
Apr 23, 2024
We explore Aerospace and Government (A&G) chip design and explain how Silicon Lifecycle Management (SLM) ensures semiconductor reliability for A&G applications.The post SLM Solutions for Mission-Critical Aerospace and Government Chip Designs appeared first on Chip ...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Enabling the Evolution of E-mobility for Your Applications
The next generation of electric vehicles, including trucks, buses, construction and recreational vehicles will need connectivity solutions that are modular, scalable, high performance, and can operate in harsh environments. In this episode of Chalk Talk, Amelia Dalton and Daniel Domke from TE Connectivity examine design considerations for next generation e-mobility applications and the benefits that TE Connectivity’s PowerTube HVP-HD Connector Series bring to these designs.
Feb 28, 2024
7,449 views