Back to Editors' Blog

Challenging PrimeTime. Really.

by Bryon Moyer

May 20, 2013 at 10:03 AM

No one ever got fired for using PrimeTime to sign off a chip. Actually, I don’t know if that’s true, but from an EDA buyer’s point of view, it might as well be. PrimeTime has been treated as the gold standard of accuracy. To the extent that, if you have a new tool that’s more accurate than PrimeTime, then it’s wrong. Why? Because PrimeTime says so.

And most everyone has backed down from that challenge. After all, if you’re going to displace the thing against which you’re being judged and which is judging you, then you have to have something besides accuracy to sell. And just like anytime you go up against a strongly entrenched incumbent, you can’t just be kinda better: you have to be enormously overwhelmingly undeniably better. Cutting some cost by 50% (or doubling some benefit) won’t cut it. I’ve always felt you have to be at least 10 times better to overcome incumbent stiction.

Well, based on a new from-the-ground-up tool done by some ex-Magma experts, Cadence has just announced Tempus, their new sign-off timing tool. And what number improvement are they touting for performance? 10x. No, I didn’t earn any consulting fees for that number. It’s enabled to a large extent by unlocking more parallelism – dozens of CPUs (multi-threaded and distributed) rather than the usual 4-8 or so.

Accuracy is still part of the deal; they’re touting path-based analysis – 10x faster than competition, around 3M nets per hour – as a more accurate approach. It is likely, though, that designers will stick with a methodology of using graph-based first (because it’s faster than path-based) and then re-doing the failures with path-based to narrow down those areas that really need work. But it’s the 10x thing they’re touting. Technically, “up to 10x.” But they also claim that they’re being conservative in their claims.

We’ll look into some more aspects of this announcement in future posts, but for now it bears noting that temerity is afoot. It will be truly interesting to see if this really takes off or ends up as a Tempus in a teapot…

Channels

EDA. Semiconductor.

 
    submit to reddit  



Comments:

You must be logged in to leave a reply. Login »

Related Articles

Optimization Moves Up a Level

Mentors RealTime Designer Rises to RTL

by Bryon Moyer

There are a lot of reasons why we can create so much circuitry on a single piece of silicon. Obvious ones include hard work developing...

Cheap Chips

ASICs for the Rest of Us

by Dick Selwood

We all know the story: ASIC starts are falling as the costs of the design tools, the mask sets and the manufacturing process are all...

Middle Child Syndrome

Is 20nm the Forgotten FPGA Node?

by Kevin Morris

28nm is a calm, mature node. Sure, everyone was excited when it was the first to reach modern price, performance, and cost levels. We applauded...

Life Under 20

New Equipment for the 1X Process Nodes

by Bryon Moyer

Were shrinking again. Were moving past the 20-nm node into the 16 or 14 realm (depending on how you or your marketing team counts it)....

A Quantum Computing Milestone

UCSB Team Achieves >99% Reliability

by Bryon Moyer

With most of the articles I write, I try to do more than just parrot what someone else said: I really try to understand what...


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register