Back to Editors' Blog

Challenging PrimeTime. Really.

by Bryon Moyer

May 20, 2013 at 10:03 AM

No one ever got fired for using PrimeTime to sign off a chip. Actually, I don’t know if that’s true, but from an EDA buyer’s point of view, it might as well be. PrimeTime has been treated as the gold standard of accuracy. To the extent that, if you have a new tool that’s more accurate than PrimeTime, then it’s wrong. Why? Because PrimeTime says so.

And most everyone has backed down from that challenge. After all, if you’re going to displace the thing against which you’re being judged and which is judging you, then you have to have something besides accuracy to sell. And just like anytime you go up against a strongly entrenched incumbent, you can’t just be kinda better: you have to be enormously overwhelmingly undeniably better. Cutting some cost by 50% (or doubling some benefit) won’t cut it. I’ve always felt you have to be at least 10 times better to overcome incumbent stiction.

Well, based on a new from-the-ground-up tool done by some ex-Magma experts, Cadence has just announced Tempus, their new sign-off timing tool. And what number improvement are they touting for performance? 10x. No, I didn’t earn any consulting fees for that number. It’s enabled to a large extent by unlocking more parallelism – dozens of CPUs (multi-threaded and distributed) rather than the usual 4-8 or so.

Accuracy is still part of the deal; they’re touting path-based analysis – 10x faster than competition, around 3M nets per hour – as a more accurate approach. It is likely, though, that designers will stick with a methodology of using graph-based first (because it’s faster than path-based) and then re-doing the failures with path-based to narrow down those areas that really need work. But it’s the 10x thing they’re touting. Technically, “up to 10x.” But they also claim that they’re being conservative in their claims.

We’ll look into some more aspects of this announcement in future posts, but for now it bears noting that temerity is afoot. It will be truly interesting to see if this really takes off or ends up as a Tempus in a teapot…

Channels

EDA. Semiconductor.

 
    submit to reddit  



Comments:

You must be logged in to leave a reply. Login »

Related Articles

FPGA-Prototyping Simplified

Cadence Rolls New Protium Platform

by Kevin Morris

System on Chip (SoC) design today is an incredibly complicated collaborative endeavor. By applying the label System to the chips we design, we enter a...

An Irregular Street Scene

Plasma-Therm Proposes Plasma Dicing

by Bryon Moyer

A silicon wafer will always be patterned with a perfect grid of rectangular dice. Its so obvious that you even have to think about...

Analog Breakthrough?

Pulsic Automates Analog Layout

by Bryon Moyer

You are now entering the It cant be done zone. But, at least for the moment, Ill ask that you relax that axiom,...

chipKITs and JPEGs

IP in Space and Open Source Board Buildin

by Amelia Dalton

It's time to break out the sparklers, an arc welder or two, and your best space suit - Fish Fry is here to celebrate! We're...

Crossbar RRAM Tweaks Nonvolatile Memory

Unique Resistive Technology Set to Challenge NAND Flash

by Jim Turley

I gotta say, memory chips are boring.

And thats coming from a guy who lives and works in the chip business. Sure, I...

Related Blog Posts

Improved FPGA Tool Results

by Bryon Moyer

Plunify tries to get the best out of FPGA design...


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register