editor's blog
Subscribe Now

A Jump in EUV Resist Sensitivity

There was an interesting presentation that happened towards the end of SPIE Litho – it seemed to catch the audience off guard, and I frankly went away with the sense that there was some confusion in the room.

The presentation discussed an experiment that was done at Osaka University as part of the overall effort to optimize EUV exposure. It all relates to this seemingly inviolate triumvirate of “RLS”: resolution, LWR (line-width roughness), and sensitivity. Improvements within these three have to come at the expense of something within these three – they form a zero-sum game.

Normally, you expose the photoresist through the mask for the entire length of the exposure. The photons create acid where they interact with the resist, and this acid provides for the selective removal of resist material during development.

This experiment changed that. The exposure was broken into two steps:

  • A short exposure through the mask
  • After 10-15 minutes, then, with no mask, just a flood of UV across the entire wafer.

The first exposure seemed to create some acid, but mostly “sensitized” the photoresist (and I frankly didn’t come away understanding what that “sensitizing” meant from a chemical standpoint). The strange thing then was that flooding with the second exposure created the normal amount of acid only in the sensitized area.

This provided about 9 times the prior sensitivity, with no apparent tradeoff in LWR or resolution.

Note that no special resists were used; these were the same resists as are currently being used.

I didn’t get the sense that they had a real handle on what the underlying mechanisms were, and it was surprising to the audience. Assuming the data are correct, it’s certainly an interesting result. We’ll have to see if anything further comes of it, or if it goes the way of cold fusion…

Leave a Reply

featured blogs
Apr 16, 2024
In today's semiconductor era, every minute, you always look for the opportunity to enhance your skills and learning growth and want to keep up to date with the technology. This could mean you would also like to get hold of the small concepts behind the complex chip desig...
Apr 11, 2024
See how Achronix used our physical verification tools to accelerate the SoC design and verification flow, boosting chip design productivity w/ cloud-based EDA.The post Achronix Achieves 5X Faster Physical Verification for Full SoC Within Budget with Synopsys Cloud appeared ...
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Reliable Connections for Rugged Handling
Sponsored by Mouser Electronics and Amphenol
Materials handling is a growing market for electronic designs. In this episode of Chalk Talk, Amelia Dalton and Jordan Grupe from Amphenol Industrial explore the variety of connectivity solutions that Amphenol Industrial offers for materials handling designs. They also examine the DIN charging solutions that Amphenol Industrial offers and the specific applications where these connectors can be a great fit.
Dec 5, 2023
17,521 views