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A Clean, Well-Lighted Place for Models

by Bryon Moyer

October 05, 2011 at 10:12 AM

Software is becoming an increasingly important element in SoCs as embedded systems are integrated into single chips. Such a chip must ship with working software, and, if it includes a platform that will run an OS and drivers and software written by the user, then even more testing is needed to prevent nasty surprises or let-downs.

This sort of testing starts at the architectural planning phase and continues down through the exercising of software on the detailed design. Initially, and for short bits of code, it can be done on a virtual platform – a model of the processing platform executing on a host computer. For longer runs of code (even simply booting Linux) that run on the actual design, an emulator is typically needed in order to get things done in a reasonable time.

In a virtual platform, at the architectural level, the models are typically SystemC. In an emulator, they will likely be the actual design (or have components of the actual design). In both cases, communication happens at the transaction level using TLM 2.0 – between models or, in an emulation scenario, between the emulator and the host.

This means that there’s a growing need for models and transactors. While they’re available today, Synopsys and others have decided that they’re too scattered, and that there is a need for a single place to go and look for (or request) models.

So they’ve created TLMCentral, an open portal for models and transactors. While Synopsys is providing the infrastructure, it is claimed to be open to anyone (including Synopsys competitors). Synopsys will participate as a model provider based on their IP business.

They’ve created the site as a general place to go not only for models, but for information and news as well. They have a forum, a blog, and a news feed.

The site is now live at www.tlmcentral.com.

More info on the press release

Channels

EDA. Embedded. Semiconductor.

 
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bmoyer I should clarify one thing here, since I've had some offline correspondence about this. When discussing the use of emulation, I referred to needing it when running the "actual design."

In my context (or in my mind) I was contrasting that to the architectural level modeling done prior to detailed design.

In other words, you should interpret "actual design" as RTL or gate-level, where the alternative to emulation is simulation (which is problematic when running through billions of cycles).
Posted on October 07, 2011 at 8:17 PM
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