In the decades-long battle between Altera (now part of Intel) and Xilinx, no title has been more hotly contested than “Ours is Biggest.” Way back in the days when real LUTs had 4 inputs, FPGA companies resorted to measuring their density with “system gates” in order to obscure the pathetically small (at the time) amount of logic that could actually be implemented in the programmable fabric of their chips. We got press releases like “Our Devices Pack Up To 4.5 Million System Gates of Logic” (meaning that you could probably build at least one highly inefficient 16×16 multiply/accumulate before you ran into utilization problems and place-and-route failures.)
Seemingly endless PR and marketing wars raged about whose LUTs packed more logic, whether a gate count multiplier was justified for a carry chain, and how many “system gates” should be counted for various non-LUT features. The elusive answer to all of this back-and-forth posing was, of course, “nobody cares,” but the war of words did provide a source of comic relief not often found in the dry world of datasheets and device specifications. Shakespeare never wrote with such farcical irony.
Those days are far behind us now. Today, the market has matured, engineers are more discerning about their reasons for designing in particular silicon solutions, and FPGA companies have evolved to a more rational tone in marketing their technology. No longer are we bombarded with “5x lower power” (whatever THAT means), or “30% more logic capacity” than “competing FPGAs.”
Wait, right? Right.
In unrelated news, Intel has announced that they are now shipping the Stratix 10 SX family which, incidentally, happens to have the world’s largest SoC FPGAs (our superlatives, not Intel’s). Are we sure these are actually The Largest? Yep. They are. The Stratix 10 SX family is made up of 10 devices, with “equivalent LE” counts (we’ll dive into those quotation marks in a minute) ranging from around 400K to about 5.5M. Each device has a dual- or quad-core ARM Cortex-A53 processing subsystem. The nearest competing family, the Xilinx Zynq UltraScale+ MPSOC EG series tops out at about 1.1M “system logic cells.” That means, for the programmable logic fabric at least, Intel has about five times as many oranges as Xilinx has apples.
The Stratix 10 SX Cortex-A53s operate at up to 1.5 GHz (similar to the Zynq devices), include up to 229 Mb of embedded memory (vs ~40 Mb for Zynq), include up to 5K DSP blocks yielding 11K 18×19 multipliers (vs 2.5K slices each containing one 28×18 multiplier for Zynq), and as many as 144 SerDes transceivers operating at up to 30 Gbps (vs 24 transceivers operating at up to 16.3 Gbps for Zynq). Yep. Stratix is definitely bigger. It is actually a completely different class of device – more expensive and larger, and consuming more power.
There are many other differences between the two families, but let’s focus first on the similarities. The marriage of programmable logic fabric with processor subsystems is a spectacularly winning combination. Far more than a simple “integration play,” combining powerful applications processors with FPGA fabric on the same chip gives a massive increase in the amount and type of connectivity available between the processors and the other associated logic, interfaces, accelerators, peripherals, memory, and so forth. An FPGA/SoC combination brings incredible capability to the table that cannot be touched by combining FPGAs and processors on your board.
Xilinx and Intel have taken strikingly different paths in the FPGA-SoC arena from the get-go, starting with the marketing. Xilinx has always been careful never to refer to their Zynq devices as “FPGAs,” preferring to position them as SoCs with advanced capabilities. Altera (Intel) embraced the FPGA label from the beginning, referring to their similar devices simply as “SoC FPGAs.” The reasoning behind this turns out to be important. The engineering community has a broad understanding of what an “SoC” is, and of what an “FPGA” is. The decision to combine these terms or not reflects the company’s view on the preconceptions attached to each, and the primary type of designer they’re trying to win.
Intel is working the audience who already understands FPGAs and wants theirs to have powerful processors. Xilinx is wooing those who are designing with processors, and may want theirs to have some programmable fabric as well. That difference permeates everything from the marketing materials to the tools to the features of the devices themselves. Xilinx Zynq devices include lots of additional SoC goodies like real-time and graphics processors. Intel FPGA SoCs (the Stratix flavor, anyway) are more full-fledged high-end FPGAs that happen to also include ARM cores.
The FPGAs themselves have some significant differences as well. Intel’s HyperFlex architecture puts a series of small latches throughout the datapath, creating something of a micro-pipeline architecture that lets the timing optimization tools balance the delays more evenly along a critical path, resulting in faster max clock frequencies. On the arithmetic front, Intel includes support for single-precision floating point in their DSP blocks, Xilinx does not but claims that they have faster fixed-point computation as a result. Depending on your application, the floating support may be extremely valuable, or it may be wasted silicon.
If you’re in the market for a high-end FPGA with embedded ARM applications processors, however, Intel’s new Stratix 10 SX is the only game in town. This is an impressive family fabbed on the company’s own 14nm FinFET process. The devices are all monolithic, so there is no added cost for advanced 2.5D packaging, and the formidable specifications of these chips should make them indispensable in numerous applications, including the company’s targeted “5G wireless communication, software defined radios, secure computing for military applications, network function virtualization (NFV), and data center acceleration.”
In the wireless applications in particular, it will be interesting to watch the adoption of Stratix 10 SX versus Xilinx’s new Zynq RFSoC, with the former being a full-fledged high-end SoC FPGA with built-in applications processors and the latter being the equivalent of a mid-range SoC FPGA with built-in RF/Analog section. For each specific application, design teams will need to weigh the larger FPGA capacity against the ability to integrate the RF section into the same device, along with cost, power, and the other usual factors.