“Call me Ishmael.” – Herman Melville, “Moby Dick”
Call me a skeptic.
There are lots of microprocessor architectures in the world. Maybe too many. There are even plenty of free and open-source processor options. Processors are like opinions: everybody has one. So why is RISC-V any different? What makes anyone think that RISC-V will be The Next Big Thing?
I’m not sure. Maybe I just haven’t caught the fever. But I do know that a lot of smart people are betting on it. They’re sure that this time, things will be different.
Chief among them is the newly appointed CEO of SiFive, Dr. Naveed Sherwani, PhD. (He’s so new, in fact, that his name doesn’t even appear on the company’s website.) Sherwani is nothing if not enthusiastic, waxing lyrical about “democratizing hardware” and “opportunities for startups” and extolling the virtues of simplicity, quick turnarounds, and new business models. The man’s a corporate evangelist – a true believer. All for a processor design that other people are giving away.
SiFive has been called “the Red Hat of hardware,” and not without reason. Like Linux, the RISC-V processor specification is open-sourced, free, and available for anyone to use. So how do you make money distributing a free product? By customizing it, supporting it, and helping other people commercialize it. You don’t sell the product, per se, because you’re not allowed to. You sell the path that allows other people to make money. You’re an enabler.
In the case of SiFive, their strategy if twofold. First, the company designs its own RISC-V processor implementations and licenses them as IP. Second, it’s an ASIC-design firm. Want to fabricate your first (or your second, or your third…) custom RISC-V chip? Need quick turnaround and don’t have a huge budget? SiFive is the design house for you.
The company specializes in RISC-V–based ASICs, obviously, and they won’t even talk to you unless you’re going to use one of their CPU implementations in your chip. Then they’ll help you integrate that with outside IP. SiFive doesn’t have a lot of in-house IP yet (no peripherals, memory controllers, or network engines – not so much as a UART, in fact), but they’re negotiating with third-party IP firms to expand their meagre portfolio. What they do have is a flexible on-chip bus called TileLink that can bridge the gap between their RISC-V processor and AHB or AXI, and from there to somebody else’s peripherals.
“Quick and dirty” is often used pejoratively (except by mud wrestlers), but at SiFive it’s practically in the company mission statement. Their intent is to be quicker, cheaper, and simpler than other ASIC houses, and they accomplish this by being… well… quick and dirty.
Want a different processor than RISC-V? You can’t. Want to choose the package? You’ve got a couple of choices. Want to pick your fabrication technology? Too bad. SiFive believes that too much choice can be a bad thing, and it streamlines its hardware options to just a very few. The message is, “We’re good at what we do, and we don’t try to do anything else.”
The company also believes that the processor itself is an enabling technology. RISC-V is so much faster than ARM’s Cortex series – so they say – that SiFive’s designers can afford to be sloppy with physical layout, thus producing a functional chip in record time. Physical layout is hard work, and it results in only marginal improvements in speed, circuit density, and power efficiency. Why over-optimize for those things when you can get most of the benefits with automated tools? It’s the old Pareto principle (the 80/20 rule) at work, producing a “minimum viable product” with the least amount of effort.
If RISC-V weren’t so fast, efficient, and simple, Sherwani says, the company couldn’t offer its ASIC services so cheaply, nor could they turn around customer designs so quickly. The fact that RISC-V is royalty-free is just a bonus.
So why will RISC-V “democratize” hardware when so many other freely available processors have consistently failed to do so? Surely saving a few pennies on royalty payments to ARM or MIPS won’t make the difference, or we’d be awash in OpenSPARC, LEON, ZPU, low-end x86, or Amber-based chips. Processors are still expensive; reducing the royalty to zero doesn’t make them free. And processors are just one of many components in the average product. You still need DRAM, batteries, power components, peripheral chips, user interfaces, and so forth.
Then there’s the cost of software development. Spending hours to develop “free” software for a “free” processor might be a colossal waste of time if the equivalent code for a more popular chip could be licensed for a few hundred dollars. The same argument applies to support: How many hours might a developer waste in tracking down problems on an open support forum, versus simply calling the vendor? On the other hand, most “real” commercial processor vendors crowd-source their own tech support the same way, so for many this one is a wash.
Sherwani disagrees. The royalties add up, especially when you’re talking about a lot of products in a big country. India, he says, has adopted RISC-V as its “national microprocessor,” encouraging universities and research entities to use RISC-V over royalty-bearing alternatives. India has a lot of people and potentially a lot of devices, he points out, so CPU royalties could spiral into the billions of dollars. By seeding development with a freer alternative, the country as a whole stands to save a lot of money.
From little acorns do mighty oak trees grow. No, wait, that’s ARM (formerly Acorn RISC Machines). Every CPU architecture started out small at some point, and making a new one freely available can only add to its popularity. If RISC-V can bootstrap itself into relevance, if it can achieve critical mass, maybe it can become The Next Big Thing. We’ll see.
Comparisons to open-source software are inevitable, and equating SiFive to Red Hat isn’t entirely crazy. You can make money selling a free product. But the danger is in taking those comparisons too far. Creating software really is free. Anyone can do it in their spare time. It costs nothing, it requires no expensive tools, and it can be distributed at no cost. Linux, MySQL, Apache, php, Android, and hundreds of other useful (and almost necessary) programs are entirely free to use, even though they represent zillions of man-hours of labor. Facebook and Twitter are free to use, too, and they certainly support large corporations. Broadcast television is free. You just need a compatible receiver and a tolerance for 30-second advertisements (or a TiVo box).
But “open-source hardware” isn’t really a thing. It’s physical and tangible, and it costs money to ship, store, and operate. You can design free processors all you want, but you can’t fabricate a single one without some expensive hardware. And the costs scale proportionately with volume, unlike with software. Making a thousand processors costs you about a thousand times more than making your first one.
SiFive has a foot in both worlds. It’s a software company, making and licensing its RISC-V IP. The company collects an up-front license fee, but there are no royalties after that. (The company’s complete license agreement is available online, here.)
But it’s also a hardware-and-services company, assisting ASIC customers with their RISC-V design, integration, layout, and fabrication. Like most ASIC firms, they collect NRE (nonrecurring engineering) fees up front, followed by per-unit piece prices. (Don’t call it a royalty.) What SiFive doesn’t offer is standard products. They don’t want to be in the fabless chip business. That’s their customers’ territory.
Plenty of firms besides Red Hat have built profitable and sustainable businesses around “free” software. And there are plenty of successful ASIC houses. And microprocessor vendors. And IP licensors (but fewer of those all the time…). There’s no reason SiFive can’t build itself up into a major player. Maybe the RISC-V processor architecture will be key to that success, or maybe it will wind up being an historical footnote, just something the company did in the early days that turned out to be a sideline. Either way, they’re hiring. So if you share Dr. Sherwani’s enthusiasm, now’s your chance.
I don’t think it is about “open source processors” – it’s about an “open STANDARD” called RISC-V. A good comparison is Verilog … it is an open standard maintained by the IEEE and there are free open source Verilog simulators available. But companies designing ASICs and SoCs use PROPRIETARY Verilog simulators that are COMPLIANT with the Verilog open standard … I can’t imagine any semi vendor risking their ASIC/SoC design project by using an open source Verilog simulator, can you?
Same is true in the RISC-V space. I don’t expect companies to use open source processors … I do expect them to use proprietary processors that are COMPLIANT with the RISC-V OPEN STANDARD.
I think you missed the point. Just like Cadence, Mentor, and Synopsys make good money selling proprietary Verilog simulators compliant with the Verilog open STANDARD, so too will the RISC-V processor vendors make good money selling proprietary processors compliant with the RISC-V open STANDARD.
Why will RISC-V be the next best thing? Because no longer will semi companies designing ASICs and SoCs be “locked into their IP vendors” such as ARM. With truly portable embedded SW and many RISC-V compliant processors to choose from, ASIC/SoC design teams can move from one processor vendor to another whenever they desire. And just like Lending Tree says about mortgages (“When banks compete for your business, you win”), the same will be true about embedded processors. When ASIC/SoC design teams are no longer “locked in” to ARM, they win.
That’s why RISC-V is a BIG THING.
Your point is well made, but I still don’t get it.
ARM users have the choice of 100+ different vendors (it seems), all of which make chips that are totally 100% compliant with the ARM architecture standard. Same goes for MIPS-compatible processors, or SPARC processors, et al.
The fact that ARM (or Imagination Technologies, etc.) is a commercial entity with control over that standard doesn’t make any difference, IMHO. Okay, so the RISC-V architecture is controlled by one group, and the ARM architecture is controlled by another group. How does that affect my hardware design? Or my choice of chip vendors? If I’m an ASIC designer, I still have zero control over the CPU architecture either way. I’m implementing somebody else’s design. (Which is fine, because I don’t want to design a brand new processor.)
We already have several CPU architectures that are defined by open, shared standards. Anyone can implement a fully compliant chip for free. Why aren’t they more popular?
Even more important is the choice of software. A commercial entity (such as ARM or Intel) can afford to sink huge sums of money into software development, which is arguably more important than the hardware architecture. Those CPU families already have “truly portable embedded software” and “many processors to choose from.”
Can the RISC-V group afford to seed that kind of software ecosystem? Will that software spring up all on its own? Will third parties jump in anyway, hoping it will pay off down the road? All of those outcomes are possible, but none is certain.
It depends on your definition of “truly portable embedded software” Jim. Most embedded software is written in C and C++. These languages care not what the underlying ISA is. My observation on the ARM ecosystem is that, yes, there is a bunch of software out there but no two ARM IC’s are alike, each and every ARM chip on the market has a different memory map. So the effort of porting code from supplier A’s ARM IC to Supplier B’s ARM chip in mind is equivalent to porting to a MIPS or RISC-V CPU. I also suspect, but cant prove, that this fragmentation in the embedded space is whats driving the popularity of embedded Linux. Once you choose to use an OS the underlying ISA truly does not matter. Something that DanG hints at is that with the standard RISC-V ISA everyone gets an architectural license. You are free to implement the underlying architecture to meet specific program requirements. And on a final note the only truly ecosystem out there in my opinion is x86.
will be happy to spend the time to spread the fever … won’t try though with a reply
I will mention one very tangible difference (but by no means the most important difference) between risc-v and ARM or x86 … unless you buy an architectural license, you cannot change the ARM instruction set and you cannot change x86 through any means … RISC-V is designed for standard and custom extensibility … and it is not a hollow use case or promise … Codasip is just one company that offers customizable RISC-V ISA processor … they not only generate the RTL, but they also generate the entire tool chain needed to use the customizable instruction … Microsemi is using this capability in a real product … see https://www.codasip.com/2017/07/13/microsemi-and-codasips-presentation-at-dac-2017/
which leads to another point, I am pretty sure IP providers that have proprietary ISAs will convert to the RISC-V ISA in droves … only by joining forces, can they participate in an ecosystem of the scale of ARM and Intel … they realize that their differentiation is not their ISA … in addition to Codasip, you will find companies such as Cortus and Gaisler have joined the RISC-V Foundation … more significantly, Andes who’s ISA is shipping in over 4.5B SoCs recently announced that their next generation ISA will be RISC-V … https://www.andestech.com/news-d.php?cls=1&id=382
SiFive is a great company and I can vouch that they live up to their productivity claims but what is more important is that their is a growing ecosystem of innovative processor IP companies all speaking a common language
the best place to start developing RISC-V code is with Microsemi’s SoftConsole eclipse based IDE which runs on both Windows and Linux http://www.prnewswire.com/news-releases/microsemi-announces-softconsole-v51-the-worlds-first-freely-available-windows-hosted-eclipse-integrated-development-environment-supporting-risc-v-open-instruction-set-architecture-300474407.html You’ll find example projects including risc-v ports of FreeRTOS and LiteOS.
as i said, if you, or your readers for that matter, wish to learn more about RISC-V, look me up
Ted Speers, Microsemi, RISC-V BoD, infected since 2014
“ARM users have the choice of 100+ different vendors (it seems), all of which make chips that are totally 100% compliant with the ARM architecture standard” is not an accurate statement to my point. You are confusing the IC manufacturer/supplier of off-the-shelf components with the IP vendor who enables ASIC/SoC design. ARM users have ONLY the choices ARM provides – in the microcontroller world that means an M0, M3, etc … it’s a finite and small choice of embedded processors. So it’s not about who is designing or manufacturing your ASIC/SoC, it’s about which processor you license to use inside your ASIC/SoC that you are designing. I think in your mind “ARM users” are embedded folks that buy off-the-shelf ARM based processors from folks like Silicon Labs, Nordic Semi, et al. That’s NOT the relevance of RISC-V … RISC-V is important to ASIC/SoC DESIGNERS who license embedded processors from folks like MIPs, ARM, Codasip, et al. I think our perspective is different about “ARM users” that use a commercial processor – again, I’m talking about designers who embed their own processor.
“The fact that ARM (or Imagination Technologies, etc.) is a commercial entity with control over that standard doesn’t make any difference, IMHO” – ARM having control over the standard is a HUGE thing, at least, according to the hundreds of companies that are now members of the RISC-V Foundation.
Why did many people use VHDL? Because Cadence “owned” the standard … once Verilog became an open standard owned by the IEEE, voila, everyone – even Qualcomm – now uses Verilog. (Ok, some FPGA and military/govt folks still use VHDL – but you can count them on your hands and toes). So, yes, inside companies who spend 10s of millions of dollars to produce ASICs and SoCs, who “owns” the standard is a friggin HUGE deal! You might want to consider why every RISC-V Workshop sells out – over 500 tickets, gone! Boom!! At Goggle last November they had an overflow room for video watching the RISC-V Workshop … and yet in your opinion, none of that matters. Wow. I met people from Switzerland, China, Singapore, India, etc who all traveled to the RISC-V Workshop … because they don’t care? Really??
And this statement is flat out wrong …. ” If I’m an ASIC designer, I still have zero control over the CPU architecture either way.” JohnGalt indeed was correct – with RISC-V everyone has an architectural license and is free to alter the architecture any way they desire to produce an OPTIMAL, not generic, processor. And the results have been shown at this year’s DAC to be impressive … Microsemi for example got a 56x improvement over ARM’s processors by extending the RISC-V ISA and using a compliant RISC-V processor. Yes – that’s 56x. Check out their DAC presentation … the data was presented in June in Austin. It’s real and it’s compelling. And they had full control over their RISC-V architecture and implementation … much to ARM’s dismay.
What this article does is promote the thinking that “all embedded processors are a black box with a datasheet”. That’s simply no longer true in the RISC-V space. Anyone can now create an optimized processor that is RISC-V compliant. It’s happening today … and you’ll be seeing the fruits of their labor very soon as RISC-V silicon hits the market. But again, these are people DESIGNING their own silicon … not like those in the Embedded World who simply buy off-the-shelf components and program them.
As to “truly portable embedded SW” – the issue JohnGalt doesn’t take into consideration is that C/C++ is only portable if the compilers exist for the embedded processors. What happens if the IP vendor shuts down and the compiler is no longer maintained? Ummm … anyone notice the status of MIPs? It ain’t good and there is a big For Sale sign on their lobby door. Yes, one could take their C code and recompile into another processor … but that’s not portable. That’s recompiled and relies on a compiler. Truly portable code is object code that just runs … no tools or recompilation required. That’s what RISC-V guarantees and it’s important to many many many companies … again, that’s why RISC-V is a BIG deal.
Would it be possible to post a link to the Microsemi DAC paper?
I did manage to find this – it has a table that mentions 56x
https://www.codasip.com/2017/07/13/microsemi-and-codasips-presentation-at-dac-2017/
It looks like they are mentioning the improvement any baseline RISC (in their table they are comparing with a RISC-V not an ARM baseline?) which you typically achieve when adding DSP extension instruction (Multiply-Accumulate / Multiword ops,etc) – and having the compiler/tools rebake eveything for you.
This sort of thing was a novelty about 20 years ago. But maybe the BIG deal here is that a lot of folks are re-learning this stuff for the first time? And getting excited about it.
Mind you – being processor agnostic is a great big deal for FPGAs – since it avoid a designer getting locked into the FPGA vendors RISC cpu flavour. But it does require somebody to grow a tailored implementation for each FPGA family to squeak the best performance out.
The whole RISC-V seems to be a bit of a NIH syndrome type of thing – (maybe Prof Patterson was annoyed at the success of ARM as he was looking at MIPs or something like that?) but it really doesn’t matter – the market will decide what it likes.
So good luck to everybody!
Keep learning!
DanG wrote:
“Ok, some FPGA and military/govt folks still use VHDL – but you can count them on your hands and toes”
FPGA designers outnumber ASIC Verilog cowboys by at least an order of magnitude.
One reason many adopted VHDL early on was the excellent VHDL language support in early FPGA tools (Synplicity/Exemplar/ModelTech).
In contrast, VHDL language support in Synopsys’ FPGA Express was best described as pathetic.
The most recent[2016] FPGA design numbers I’ve seen had VHDL & Verilog about evenly split:
https://blogs.mentor.com/verificationhorizons/blog/2016/09/21/part-6-the-2016-wilson-research-group-functional-verification-study/
For hardware design, I still prefer VHDL/Verilog synthesis over any of the new-fangled re-inventions (“Hey! let’s use C”, or “Hey! Let’s embed a structural netlist generator in a functional language!”), although I see some uses for the HLS stuff in what I think of as ‘algorithm acceleration’.
-Brian
I don’t know much about processor ISAs but does RISC-V help make software development easier than on ARM-based boards?
My experience with anything ARM is that no 2 boards are initialized the same, you may never get newer Linux kernels working which is also related to missing/outdated drivers. It’s a pretty bad experience working on anything with an ARM SoC. I’d take an x86 board any day except they’re too power hungry.
Does RISC-V help address any of these issues?