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QuickLogic Heats Up eFPGA

Putting Programmability into Low Power Designs

We’ve written several times now about the numerous advantages of putting FPGA fabric into your ASIC or SoC, rather than parking an FPGA next to it. Most teams designing custom chips these days have some kind of need for the flexibility of programmable logic, whether it’s to manage connectivity with a diverse or changing set of interfaces, perform compute acceleration for complex tasks, fuse data from multiple sensors, or any number of other operations that can’t readily be poured into the concrete of hardened logic. Having a few (or sometimes even a lot) of LUTs lying around can cure a world of issues in the high-risk, high-investment world of custom ICs.

If you crack apart most systems today that have a custom ASIC, ASSP, or SoC, you’ll find some kind of FPGA sitting right next to that custom device, giving that little bit of needed hardware programmability. But adding that FPGA comes at a big cost. First, there is the BOM cost. FPGAs are expensive, and the folks who sell them are proud of their margins. That means you’re always looking at a costly piece of silicon. Second, there is the additional complexity and size in your PCB, with (at least) one more chip and one more set of traces to route, pick, place, solder, and test.

Using embedded FPGA IP in your custom chip can solve those issues. If you know about how much LUT fabric you need, you can put it into your chip at a fraction of the cost of parking an actual FPGA next to it later. But the benefits don’t stop there. Because all of your SoC-to-FPGA communications are now on chip, you don’t have to pay for pins, traces, and the associated power and performance loss from chip-to-chip connections compared with on-chip connections. And, you can make far more connections between the FPGA part and the other parts than would be possible using normal IO.

A number of companies have now entered the embedded FPGA IP business. We’ve written recently about Flex Logix and Achronix – both of whom are attacking the larger-scale LUT arrays. But, on the small end of the spectrum, QuickLogic has a robust and proven eFPGA offering that is ideal for applications that require very low power consumption and smaller arrays of LUTs. QuickLogic is targeting teams who want to increase ROI by creating multiple variants of a chip with a single set of masks, to add different feature sets, or to support different configurations of IO and peripherals in an SoC with ultra-low power requirements.

QuickLogic’s ArcticPro eFPGA has already been proven in several foundry partners, and the company has had significant experience taping out their own FPGA, ASSP, and SoC/FPGA devices over the past several decades. Their expertise in designing and shipping their own devices is likely to pave a smooth road for teams who are adopting their technology, and their well-established design tool chain should be a major asset to teams wanting to configure their embedded FPGA fabric.

The company has two eFPGA offerings: ArcticPro, and ArcticPro 2. ArcticPro has a fine-grained architecture designed for high logic-cell utilization and ultra low power consumption. The basic logic cell can implement two LUT3s or one LUT4, an 8:1 mux and an independent 2:1 mux, and an optional flip flop. This flexibility in cell configuration allows more efficient synthesis and maximizes logic and utilization for a given array size. Speaking of array sizes, you can add arrays ranging from 16×16 cells up to 64×64 cells, bringing a significant amount of programmability into your hardware. There also appears to be no reason you couldn’t have multiple arrays on a single die if, for example, you needed one array to implement flexible peripherals/interfaces and another to do always-awake sensor fusion while other islands of your chip are in a power-saving standby state.

ArcticPro 2 is similar to ArcticPro, but it is optimized more for performance with low power, rather than ultra low power. ArcticPro 2 uses a Super Logic Cell (SLC) structure where each SLC consists of 4 Logic Cells (LCs). Each LC can be used as 2 independent LUT4s, or one LUT5. Direct input selection to the register allows combinatorial and sequential logic to be used separately. Multiple outputs per SLC are strategically selected either to feed back into the same SLC, or to branch out to another SLC.  A shared register clock and set and reset signals for all four logic cells helps to reduce routing congestion, and two carry-in mixes per cell allow each cell to function as a 2-bit adder, giving the possibility of an 8-bit adder per SLC.

On the power reduction front, ArcticPro has a special “very low power” (VLP) sleep mode, which significantly reduces power consumption by placing the device in standby. The device can enter/exit VLP mode in less than 100 microseconds, and all register values are preserved during the use of the standby circuit. In 40nm technology with a 32×32 LC configuration, current in VLP mode is a stingy 30 microamps.

For IO, ArcticPro features high bandwidth interface buffers with both registered and non-registered path signals, under the control of the Aurora device configuration tool. When your eFPGA core is powered down, isolation buffers take care of business with the rest of your circuit.

Configuration works very similar to a standalone FPGA. The controller is a separate RTL block that can be connected to multiple interfaces such as SPI, I2C, UART, and even AMBA bus. For example, when connected to an SPI master, the configuration controller uses around 30K ASIC gates, so configuration of the FPGA presents very low area overhead to your overall design.

QuickLogic has developed a compiler that automatically creates the desired array configuration for your design, allowing the array to be customized for your application. The LUT array requires no special process steps or modifications, and it works with a variety of commodity semiconductor processes. In addition to the compiler, QuickLogic supplies a complete suite of tools, with synthesis and place-and-route, for developing the contents of the FPGA fabric,. Standard RTL development tools (such as simulators) can be used for the FPGA portion of the design.

It will be interesting to watch the evolution of the eFPGA market and the effect it will have on the mainstream FPGA market. Xilinx and Intel (Altera) are working hard to expand the overall market for programmable logic technology, and they are counting on being the go-to solutions when hardware programmability is required. If embedded FPGA technology catches on, it has the potential to strip a lot of valuable sockets from conventional FPGAs, which would otherwise be sold to park alongside custom chips. Companies like QuickLogic, Achronix, and Flex Logix are all working to make that vision a reality.

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