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LSI Logic’s Leverage

What has over two million real ASIC gates, runs at over 200MHz with twenty levels of logic, burns about the power of a cell-based ASIC, and is economically feasible to deploy even in mid-to-small volume production? The answer is “Not an FPGA”. While these specs may sound close to the marketing picture painted by programmable logic vendors, there is a vast gulf between the brochure and real-world performance in an average application. Structured and platform ASICs, however, can realistically reach these goals in your average application, and getting design teams to understand that fact is one of … Read More → "LSI Logic’s Leverage"

Ditchin’ DAC

From before my kids were born until after they were grown and graduated, it was a June ritual. Twenty-one times in all, I made my annual pilgrimage to the Design Automation Conference (DAC), perhaps the most misunderstood massing of technology professionals our industry has to offer. DAC is “Burning Man” for the left brain – a mysteriously gravitational gathering that inexplicably pulls people from around the globe to one central location in non-consensual celebration of the unclear.

This year, the 42nd annual DAC was held in Anaheim California. It featured 240 exhibitors, 60 of whom were showing … Read More → "Ditchin’ DAC"

What the Hell is ESL?

The tool category known as “Kitchen Appliances” covers a wide gamut of capabilities. Kitchen appliances range from general-purpose, universally useful tools such as heat sources, to highly specialized, perhaps less-than-indispensable technologies like “in-the-egg scramblers”. If someone tells you that his or her tool is a kitchen appliance, you haven’t really gained any useful information about its utility for your particular application.

The design tool category known as “ESL” has similar characteristics. When someone tries to sell you an ESL tool, it’s never quite clear what you’ … Read More → "What the Hell is ESL?"

FPGAs Enabling Consumer Electronics – A Growing Trend

It was in the late 1990s that FPGA vendors first started exploring the low-cost, high-volume consumer market – a market that generally was ceded to standard, fixed-function devices. Exploring this market was made possible by the development of FPGAs with the right balance of features and the migration to advanced process nodes which helped to drastically reduce FPGA unit costs.

Historically for high-volume, price-sensitive applications, FPGAs were not the lowest-cost solution. However, as custom logic and FPGAs started to get pad-limited vs. core-limited, this started to change. Pad limitation occurs when the size … Read More → "FPGAs Enabling Consumer Electronics – A Growing Trend"

Are These Guys Dense, or What?

Context can drastically impact the meaning of a simple word. If you’re walking down the street minding your own business, you might find yourself feeling more than a little bit offended if someone calls you dense. You may even experience a brief but painful flashback to that dreaded walk through the gauntlet of cool kids lining the halls in school, hearing any number of rude, if inaccurate, comments (after all, who’s calling who dense?) thrown with casual abandon in your direction. Now, change the circumstance. You’re at a tradeshow, … Read More → "Are These Guys Dense, or What?"

Accelerating C Software Applications Using a CompactFlash FPGA Accelerator Card

As the cost per gate of FPGAs continues to plummet, developers of embedded software applications are being presented with increased opportunities to create high performance, hardware-accelerated systems. These systems—which represent applications in domains ranging from image processing and DSP to larger-scale applications for scientific computing—benefit from the massive levels of parallelism that are available when FPGAs are used as alternatives to traditional processor architectures.

This article describes how the convergence of easier-to-use, more powerful FPGA-based computing platforms and software-to-hardware design tools can make the design of accelerated FPGA-based algorithms easier and more practical … Read More → "Accelerating C Software Applications Using a CompactFlash FPGA Accelerator Card"

Shrink-wrapping EDA

When I bought my first 10MB hard-disk drive, the salesman came to visit and even took me out to lunch. I was a freshman in engineering school and I was buying the $10,000 unit for my employer, a hotel chain, to use for storing reservation data. At the time, a purchase of that amount of mass storage was a major transaction, both for our little company and for our supplier. The disk drive, about the size of a modern desktop computer, was delivered and installed by a trained technician who spent an hour with us going over the operating procedures … Read More → "Shrink-wrapping EDA"

Core Sample

The preparation starts weeks in advance. Whole grains are stone-ground – the resulting flour combined with honey extracted from backyard beehives over a period of months. The dough is then pressed and baked on hand-forged pans in wood-fired ovens until a fine golden crust appears that can be crushed into flakes of exactly the right consistency. After cooling, the flakes are poured into handmade pottery bowls, fired the previous week after being slung from native clay dug from the local riverbed. Finally, right before breakfast, milk from cows raised on grain grown in your own field is poured over the … Read More → "Core Sample"

Redefining Structured ASIC

In most markets, there exist a set of de-facto rules. Sport-utility vehicles have bad fuel economy. Economy cars have limited cargo space. FPGAs use too much power. ASICs have staggering non-recurring engineering (NRE) costs. Generally, the players play by those rules, and the consumer enters every buying decision with a pre-defined understanding of the tradeoffs those rules imply and which basic option favors their situation. The final choice is then decided by a comparison of the less-critical factors that differentiate the products in each area. Once a design team has decided to go with a zero-NRE solution, for example, … Read More → "Redefining Structured ASIC"

Selecting the FPGA that Meets Your Signal Integrity Requirements

In light of its critical nature, signal integrity needs to be a key criterion during the planning and design phases of high-speed systems. Ignoring signal integrity can lead to poor reliability, degraded performance, field failures and delayed product releases—all of which can trigger lost opportunities and revenues.

Today’s high-end FPGAs support a variety of single-ended and differential I/O standards, with options to control drive-strength, slew-rate and on-chip termination. If not used correctly, this flexibility offered by FPGAs can make it difficult to manage signal integrity. Selecting the right FPGA that … Read More → "Selecting the FPGA that Meets Your Signal Integrity Requirements"

featured blogs
Oct 17, 2018
This week it is CDNLive Israel. But last week it was Jasper User Group (JUG). At it happens, Jasper was one of the early companies to sign up with SemiWiki when we started it, so I've been going to Jasper User Group for longer than either I've been at Cadence or Jas...
Oct 16, 2018
EDI CON USA brings together RF, microwave, EMC/EMI, and high-speed digital design engineers and system integrators for networking, product demonstrations, training, and learning opportunities. And as you have probably already guessed, Samtec will be attending EDI CON.  We wi...
Oct 16, 2018
  IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts yet another nail into the coffin for poor old Moore'€™s Law. Now please take care. There'€™s a vertical line between the 200mm wafers on the left ...
Oct 12, 2018
At the end of the day, your products are only as good as their in-the-field performance. It doesn'€™t matter how well they performed in a controlled environment....