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Structured ASIC Starting Line

If the value of structured ASIC as a gap-filler between programmable logic and cell-based ASIC is still in question, there are at least two companies on opposite sides of that gap where a decision has clearly been made. Both LSI Logic and Altera unveiled new families this week aimed at attacking this new and potentially lucrative segment of the silicon landscape. Interestingly, both companies’ involvement in structured ASIC can be viewed as a defensive move. As a leading supplier of cell-based ASICs, LSI shored up its defenses against attack from the other side of the FPGA/ASIC … Read More → "Structured ASIC Starting Line"

Flash News Flash

Could this be the iPod of FPGA families? Has Actel created the happy little “chip that could” to take on the SRAM-dominated titans of the low-cost FPGA battlefield? Will ProASIC3 Development boards be proudly displayed on the desks of any development team that wants the nice, clean look and feel of a secure, single-chip, ready-at-power-up, low-power, no-hassle solution to their high-volume, middle-of-the-technological-road design problem?

Like other programmable logic vendors, Actel has noticed that cell-based ASICs are becoming an increasingly specialized solution for high-volume electronics products. Only the best-funded, most risk-immune, highest-volume-and-performance applications can realistically justify … Read More → "Flash News Flash"

Accelerating Processor-based Systems

Designing an efficient processor-based system architecture with overall system performance optimized for a specific application is not trivial, requiring skills and technology similar to those employed by supercomputer designers. Accomplishing this feat requires new tools and methodologies to augment the EDA flow for both traditional ASIC design and the new class of programmable SoCs, e.g., FPGAs. Architectures and performance must be verified early in the design cycle; the designer cannot wait until RTL development to discover their architecture does not support their system requirements.

Problems to Solve

Current processor tools have not kept up … Read More → "Accelerating Processor-based Systems"

Leading Languages

I still check occasionally on gizmodo.com or engadget.com, but I’ve pretty much given up hope. It’s now 2005. Throughout my childhood, I was convinced that by this year I’d be flying around in my jetpack, or at least driving my flying car. My personal robot is a bit closer to reality, but still not in the cards for the foreseeable future, unless I just want my floors vacuumed. The one-MIPS supercomputer I had visualized in my basement, however, complete with dumb terminal and tape drives, has far exceeded expectations.

Our view … Read More → "Leading Languages"

Deliver Products On-Time with RTL Hardware Debug

Crunch time on projects always seems to come during lab debug. That’s when the FPGA, software and PCB all come together for the first time. It’s also the last, and frequently, most difficult phase in the project. Any slack time in the schedule has long since been eaten up by unanticipated delays of one sort or another. The entire team has to work together on the same thing and in the same place, possibly for the first time.

Many developers put off thinking seriously about the latter stages of the project … Read More → "Deliver Products On-Time with RTL Hardware Debug"

Debug Dilemma

What goes in software, and what goes in hardware? In most complex digital designs, the answer to this key question will determine success or failure of the architecture of the system. Put the wrong piece in software and performance suffers from overloading the processor. Put the wrong piece in hardware and your cost rises from the additional gates, static power consumption goes up, and flexibility and maintainability of the system drop significantly.

It turns out that the software versus hardware battle is going on in parallel in your design environment as well. With modern FPGA development boards, … Read More → "Debug Dilemma"

FPGAs Supplant Processors and ASICs In Advanced Imaging Applications

Proponents of the Field Programmable Gate Array have fought for years to overcome the “stepping stone” mentality with which the traditionalist engineering community has viewed the FPGA. Used primarily as either an ASIC prototyping platform or as a time-to-market stopgap until the company can produce a processor-based or ASIC-based system, the FPGA has only begun to prove its worth as an end-product solution.

To some extent, the problem has been choosing the right battleground. FPGAs have a very specific set of value propositions which, when taken together, will easily supplant ASICs and processors in the right application. … Read More → "FPGAs Supplant Processors and ASICs In Advanced Imaging Applications"

Fresh Findings

As programmable systems become increasingly complex, a rich ecosystem of technology is growing up to support the diversity of new designs that take advantage of the flexibility and time-to-market advantages afforded by today’s FPGA platforms. Every time the market presents a new opportunity, another startup or established player steps forward with a solution that advances the state of the art. Let’s examine a few of the more recent ones in detail, starting from the beginning of the design process and walking through to the working hardware.

Design Melée Management Read More → "Fresh Findings"

What’s Time to a Pig?

The efficiency expert stopped several mornings in a row on his commute into the city, pulling his car onto the shoulder of the road alongside the farm with the small apple orchard. He watched in amazement, even getting out his binoculars to be sure, as the farmer carefully lifted a full-grown pig out of the pig pen, carried him down the path to the orchard, and then climbed the small step-ladder, lifting the pig over his head and waiting patiently while the pig ate a few apples from the tree. The farmer then returned the pig to the pen, … Read More → "What’s Time to a Pig?"

3rd Party ETA

Why would you spend tens of thousands of dollars on commercial electronic design automation (EDA) tools for your design team when they can get a decent suite of tools almost for free from their FPGA vendor? This question is probably asked daily in design teams around the world. As you might expect, it also comes up every now and then in the strategic planning rooms at EDA companies. The EDA company version of the question has a slight twist, however: “Should we invest millions to develop FPGA tools if FPGA vendors may be giving away similar tools almost … Read More → "3rd Party ETA"

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...