feature article archive
Subscribe to EE Journal Daily Newsletter
5 + 5 =

Virtex-4

In the 90s, it was obvious that within the decade, exploding gate counts would outstrip our ability to design. The popular debate topic at that time was how the “white space” would be used. “White space” represented the difference between the number of available gates on a semiconductor device, and the number of gates we could successfully design correctly using current methodologies. Speculation ran rampant that large amounts of RAM, immense IP blocks, and system-on-chip integration would help us fill some of the space, but the overall question remained.

When FPGAs burst onto … Read More → "Virtex-4"

Leveraging On-Chip Debug for VME

Introduction

Galileo Avionica needed an easy-to-use VME BUS monitor that could be used by both hardware and software engineers working on VME-based projects. Using a plug-in VME board with an Altera FPGA, embedded DiaLite virtual instrumentation from Temento Systems, and a TCL/TK-based custom human interface, an innovative solution was crafted that allows simple, multi-use analysis of the VME bus by engineers from different disciplines with widely varied levels of experience and expertise.

This article describes how DiaLite Instrumentation (DLI) was used to build a custom tool by taking advantage of the capability … Read More → "Leveraging On-Chip Debug for VME"

Catapult C

Electronic design automation has its own secret little cold fusion. An innovation that everyone quietly hopes is possible but publicly disavows. A development that would make life beautiful, dogs and cats live happily together, and money grow on trees. This missing link is “behavioral synthesis,” the direct compilation of untimed algorithmic descriptions into practical hardware architectures. Once this is possible, digital hardware designers, the micro-architectural mavens that create much of the magic in today’s ASIC and FPGA designs, will no longer be necessary. All of their relevant expertise, tricks and techniques will be … Read More → "Catapult C"

FPGA Simulation

When someone uses the words “verification” and “FPGA” in the same sentence, I’m always suspicious. In the ASIC design world, where risk avoidance is everything, “verification” is a sacred term. “Verification” is the long pole in the tent, the most time-consuming phase of the design cycle. “Verification” is what you do to protect your job so you’re not blamed with an expensive and time-consuming re-spin of an ASIC design. “Verification” is what EDA companies have learned to trust as their bread-and-butter. … Read More → "FPGA Simulation"

featured blogs
Jan 15, 2018
It was CES last week. Generally, this is not an event about mobile, mainly because the big show for that industry is Mobile World Congress (MWC), which takes place in Barcelona a month or so later. For the last couple of years, I have attended and written about it. This year,...
Jan 12, 2018
Wow. What a fun year for Samtec.com and the entire team behind it! In 2017, we streamlined your online sampling experience, brought you a way to view detailed information about any of our trillions of part numbers, built an entirely new on-site search, upgraded to Azure CDN a...
Jan 5, 2018
When visitors to CES 2018 want to travel to the Las Vegas Convention Center across town, it will likely be in a fully autonomous vehicle from Lyft getting them there. While this futurist trip will certainly be a first for many riders, this type of point-to-point travel will s...
Jan 10, 2018
Recently, Electronics Products Magazine announced their 42nd Annual Product of the Year award winners, with Cadence Design Systems winning for their Virtuoso® System Design Platform. According to the article, the editors “have chosen [products] they......
Jan 15, 2018
This is the seventh in a series of blog posts showcasing the winning designs from the 27th Annual PCB Technology Leadership Awards. The 1st place winner in the Telecom, Network Controllers & Line Cards  category is Altice Labs, Portugal. This Switching Matrix card is a...