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Lattice Joins the Fray

The elite party of 90nm high-performance FPGA suppliers has just been crashed. The two big burly guards at the entrance to the VIP room were evidently not paying attention, because Lattice Semiconductor just waltzed right in – as if anybody that wanted to could whip up an FPGA family with 3.4Gbps SerDes transceivers, 2Gbps parallel I/O, up to 115K LUTs, loads of hard IP, and up to 500MHz fabric performance. Did nobody notice those 300mm wafers in their pockets?

For about a year now, only Xilinx and Altera have claimed turf in the 90nm FPGA arena. … Read More → "Lattice Joins the Fray"

MIPS Goes Multithreaded

Although most designers don’t often consider it, there are different formulas for best overall system performance from embedded and stand-alone processors, too. Even though there’s no governing league making and changing the racing regulations, parameters like total system cost, power consumption, memory bandwidth, silicon area, and process profile rule the day when choosing a processor for your system design. The tradeoffs that make the best mix of performance on standalone processors can be completely different than those that give the best results in an embedded processor core.

When MIPS designed their new 34K … Read More → "MIPS Goes Multithreaded"

Reconfigurable Computing in Real-World Applications

Developers have long been intrigued by the potential of reconfigurable computing (RC) to accelerate some computationally-intensive high-performance computing (HPC) applications. But the barriers to achieving the order-of-magnitude performance gains RC can theoretically provide are well known: the complexity of programming for RC devices and the limitations of the hardware and software traditionally used to support them. As a result, software developers have focused on fine tuning applications to run faster on standard microprocessors, and have achieved important percentage gains.

Now, emerging systems like the Cray XD1 are bringing RC application acceleration into the … Read More → "Reconfigurable Computing in Real-World Applications"

Planning Ahead

It’s a cold February morning in a well-hidden corner of Silicon Valley. The air is perfectly still. The sun is just rising above the hills, although it isn’t clearly visible through the dissipating ground fog cast over the region by the bay. There is a light frost on the grass, even though the temperature has been in the 40s all night. That’s one of the big issues with fictional, metaphoric introductions to technical articles – continuity problems. These things clearly would never stand up to an engineering design review.

Read More → "Planning Ahead"

Taming Embedded Multi-Core on FPGAs for Packet Processing

Many companies with projects involving packet processing work exclusively in software, predominantly C. They have infrastructures and methodologies based around software. They have hardware groups that provide them with the boards and systems they need, but see the bulk of their value in software. These companies do not want to learn RTL or use a hardware design approach; they want to work in C using a software approach. As a result, they have not included FPGAs in their consideration of packet processors.

Going after flexibility

One of the main benefits to using a … Read More → "Taming Embedded Multi-Core on FPGAs for Packet Processing"

Taming Embedded Multi-Core on FPGAs for Packet Processing

In public discussions about embedded multi-processing and FPGAs, most of the focus has been on DSP. But there’s another application area requiring embedded multi-processing that has remained elusive, not because of silicon deficiencies, but due to the lack of an easy methodology. That application is packet processing. Packet processing performance as high as 10 Gbps is possible in FPGAs, so the silicon is fast, but even single gigabit performance has required RTL and a hardware approach to design.

Many companies with projects involving packet processing work exclusively in software, predominantly C. They have infrastructures and methodologies … Read More → "Taming Embedded Multi-Core on FPGAs for Packet Processing"

Status Quopia

“You don’t understand,” my father patiently explained. “People have enormous collections of vinyl records. They’re never going to switch to a new format like compact disc, even if the sound and convenience are better. There’s just too much already invested.” Generally, Dad was a progressive, technically-savvy, keep-up-with-change kinda’ guy. On some issues, however, he just couldn’t see past the status-quo. His experience had built a level of technology-rooted myopia that his vision couldn’t overcome. When the new thing came along, even though … Read More → "Status Quopia"

Getting Performance with Memory Protection in Real-time Windows Systems

Development using Ring 3 provides the benefit of memory protection from the application, which aids in debugging the application by letting the hardware catch common programming errors. This enables rapid development, because in many cases, only the application will crash upon hitting a bug. With the operating system running, the application can be restarted and the debugging can be continued – resulting in a quick test, debug and fix cycle.

However, this does not hold true during deployment. A real-time system, by its very nature, requires the application and the operating system to be fully functioning and stable. … Read More → "Getting Performance with Memory Protection in Real-time Windows Systems"

This Engineer Walks Into a Bar…

We’ve all had our moments. If you hear that your blind date has a great sense of humor, perhaps you develop a preconceived notion about said date’s outward appearance. What if you were told that your date was an engineer?

The stereotype that brands engineers as nerds is clearly defined. It’s reached a level of stability and adoption that could qualify it for ratification by the IEEE. It could be known as the “Nerd Classification Code,” or NCC-1701. Over the years, creative jokesters have found ever more amusing ways … Read More → "This Engineer Walks Into a Bar…"

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