Step right up! Who feels lucky? Find the money card and win! Moore’s Law is a fickle beast. After fifty years of consistent behavior, it seems the old Law has finally gone a bit off its rocker, and nowhere is that hitch in its git-along more pronounced than in the FPGA world. Now, figuring out who’s on which node first and what it means is like trying to win at 3-card Monte when you’re not running the game. Nonetheless, new news has broken and we’ll try to help sort it all out. Just find the lady…
This week, the latest round of the FPGA node game officially began, with Intel dropping a preview of an upcoming high-end 10nm FinFET FPGA family code-named “Falcon Mesa” during their “Intel Manufacturing Technology Day” in Beijing, China on Sept 19. While details are scant and questions are plentiful, here’s what we know about the next installment in the Altera/Intel “Stratix” saga. (We don’t know, for example, whether Falcon Mesa will be called “Stratix” in production. In truth we always find Intel’s internal code names far more memorable and interesting than final product names anyway.)
Intel says Falcon Mesa FPGAs will “target the acceleration and compute needs in data center, wireless 5G, network function virtualization (NFV), automotive, industrial, and military/aerospace applications.” Or, in other words, the usual markets that high-end FPGAs target these days. We can’t help but think that Intel will be building with a bias towards their most important markets, which means we’d expect to see Falcon Mesa be pretty data-center and AI friendly when the details finally emerge.
Let’s start with the basics – the process node. Falcon Mesa will be built on Intel’s 10nm FinFET manufacturing process technology. According to some, 10nm is infamously late at Intel, originally promised for the end of 2015 but now slated for early 2018 (that’s for first shipments of any devices on this process, but we don’t have a schedule for Falcon Mesa FPGAs yet). That would be more than a two-year delay, which some news outlets claim was fueled by distractions related to Intel’s struggles with the current 14nm FinFET node.
Intel tells a different story, of course. Back in March, we wrote about Intel’s previous “Intel Technology and Manufacturing Day”, where the company gave fascinating insight into their process technology strategies and details. While Intel has historically been highly secretive about their semiconductor processes, the current push of contract manufacturing forces the company to be more transparent about what’s going on in the fabs.
Intel admits that the historical 2-year clock on Moore’s Law has now relaxed to more like 3 years. The company has responded to this by replacing the so-called 2-year “tick-tock” release of process variants with a 3-year “tick-tock-tock.” 10nm, for example, is followed by 10+ and then 10++. Each process variant has different power/performance characteristics, but is built on the same scaling as the original. According to that plan, 10nm is right on track.
What does that mean competitively? Well, FPGA rival Xilinx (who uses TSMC for manufacturing) announced way back in 2015 that they would be skipping the TSMC 10nm node entirely. Altera skipped 20nm for their Stratix family, going directly from 28nm to 14nm, so the two rivals have been in a bit of a leapfrog mode on process nodes – according to the names, at least.
Xilinx has long maintained that their first 7nm devices would be ready by early 2018 (but no specific announcement has been made yet, except for a TSMC, ARM, Cadence, Xilinx CCIX test chip planned for early 2018). Even though Intel/Altera is not giving a timetable, it is possible that Xilinx will be shipping “7nm” TSMC-fabbed FPGAs at nearly the same time Intel begins shipping “10nm” Intel-fabbed FPGAs. That would appear to be a one-node lead for Xilinx. However, because of the vague way that new process nodes are named these days (just try finding something that actually measures 7nm on a “7nm” FPGA), it isn’t really clear what the value difference (density, performance, power) will be between TSMC 7nm and Intel 10nm.
Confused yet? Watch the money card…
Back in the March event, however, Intel’s Mark Bohr gave a talk titled “Let’s Clear Up this Node Naming Mess,” in which he (and Intel) proposed a new way to keep score on node names. Rather than using the current (and completely arbitrary) 14nm, 10nm, 7nm titles, Bohr says we should focus on the real meaning of Moore’s Law: component density, measured in million transistors per mm2 (MTr/mm2). According to Bohr, that puts Intel’s similarly-named processes about 3 years ahead of competitors’. In other words, Intel 10nm would have a density comparable to TSMC 7nm.
Convenient, eh? Keep your eyes on the queen…
Intel says the Falcon Mesa FPGA fabric itself will include a new 10nm version of the HyperFlex architecture, which uses registers called hyper-registers throughout the FPGA to improve timing closure by essentially creating micro-pipelines. IO-wise, Falcon Mesa will feature 112 Gbps serial transceivers supplied by Intel’s merchant fab team (in the past, the Altera team has done their own transceivers), PCI Express Gen4 x16 with data rates up to 16 CT/s per lane, and a second-generation version of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) packaging technology, putting “higher levels of transceiver performance alongside a monolithic FPGA fabric,” and next-generation High-Bandwidth Memory (HBM) support.
OK, hang on a minute. This is where things start to get tricky.
One of the big benefits of heterogeneous multi-die packaging is that you can mix dies from different process technologies into a single package, choosing the process that gives the best benefits for each one. While it appears that the FPGA fabric will itself be using Intel’s 10nm FinFET process, the transceivers and other IO features will likely not. While no public info on the 112 Gbps transceivers has been released yet, it seems that Intel is already offering them to their manufacturing foundry partners. We’re guessing they will be some kind of PAM4 or PAM8 technology built on a more analog-appropriate process.
Regarding the HBM, Intel carries a lot more weight with the memory manufacturers than Altera did in the past. As a result, expect the HBM (HBM, HBM2 gen 1 and 2, and eventually HBM 3) stacks to be the best available, packaged in the FPGAs alongside the FPGA fabric using EMIB and UIB.
Transceiver, PCIe, Ethernet, and HBM integration are where the Intel EMIB really shines, as the company can create a huge variety of FPGA packages using a single taped-out version of the FPGA fabric itself. That means they can customize the IO and memory capabilities for various markets at the packaging level without having to do multiple tape-outs for the FPGA fabric.
Intel really hasn’t told us much about their actual FPGA plans for Falcon Mesa. We have no idea yet of FPGA stats such as density range, performance expectations, hard IP such as embedded DSP and floating-point blocks, and embedded memory. Our expectations would be the usual node-to-node gains on all fronts: something like a doubling of density, marginally higher operating frequencies, and proportionally less power consumption for a given application. Interestingly, Intel did reference “monolithic” when describing the FPGA fabric, so we are led to conclude that Intel/Altera will continue to build their largest devices as single monolithic die, where Xilinx constructs their largest FPGAs from several smaller dies connected via an interposer.
We also don’t have a delivery schedule. In the Altera days, when we had an announcement with this little detail, we were still a couple of years from first device shipments. In this case, we suspect the timeline is much shorter. In short, Intel is playing this one close to the vest.
Ready to pick a card?