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Cypress Tames Two-Headed Monster

M4 + M0 Equals More

“While my friends were busy listening to the Talking Heads… I was busy teaching myself to program on the Atari.” — Steven Sinofsky

What would you do with 104 I/O pins, two CPU cores, two 8K caches, a touchscreen interface, Bluetooth, four AA batteries, and a gaggle of analog components? You may be about to find out.

Cypress has upgraded its programmable system-on-chip (PSoC) family of flexible microcontrollers with a new dual-core, security-enhanced, low-power family it calls PSoC 6. It’s the first dual-core chip from Cypress, and the first to use ARM’s Cortex-M4 processor. Previous generations of the PSoC used either the M0, the M0+, or the M3. So, upgrading to the M4 core is a step up, and adding an M0+ is a step-upper.

They’re fast CPU cores, too. The M4 runs at 150 MHz, which is a pretty good clip for an MCU. For its part, the M0+ core tops out at 100 MHz, also quickish for what is basically a glorified programmable peripheral controller. Between the two of them, the M4/M0+ pairing offers decent programmable performance to go along with the big collection of hardware peripherals.

As the name might suggest, PSoC chips are intended to be standalone, system-on-chip devices that combine all of your CPU and I/O needs into one, along with a dash of programmable logic. Like previous PSoC devices, these ones include a mini-FPGA for random logic, as well as programmable analog blocks, including op amps, A/D and D/A converters, comparators, and the company’s patented CapSense interface for touchscreens.

The wealth of on-chip peripherals, both the hardwired kind and the programmable/configurable kind, are shared between the two ARM cores. Controllers and interfaces don’t “belong” to one CPU core or the other; they’re pooled and can be controlled by either the M4 or the M0+, as the programmer wishes. There’s even some inter-processor communication (ICP) features in the PSoC 6 to make this sharing economy less taxing.

On the other hand, you can also “core lock” peripherals to one CPU core or the other as a security measure. If you’ve got the M0+ managing the USB interface, for example, you may not want the M4 core fiddling with it under any circumstances. Any unwanted advanced from the M4 side would be flagged as a security violation.

Cypress has also gotten aggressive(-ish) with its fabrication technology. PSoC 6 devices are fabbed in a new 40nm process, which is within shouting distance of the leading edge of today’s semiconductor technology, at least for a low-cost microcontroller. For comparison, the company’s other MCUs are built in a well-worn 130nm process.

Cypress is quick to point out that the new 40nm process is its own technology. Even though the chips are physically produced by UMC in Taiwan, the process technology was developed, in part, by Cypress and includes Cypress IP, making it transferrable (at least, in theory) to other third-party fabs. That’s unusual for MCU makers, who generally rely on whatever bulk, high-yield process their fab partner is currently running.

The relatively advanced process makes the chips smaller, of course, but it also makes them more power-efficient, which was Cypress’s real goal. The company very much wanted to leapfrog NXP, Microchip, TI, Silicon Labs, and approximately a thousand other MCU makers by offering a high-performance MCU that could also last for weeks or months on a single battery charge.

To that end, the PSoC 6 chips offer an assortment of now-familiar power modes that selectively shut down parts of the chip, throttle clocks, hibernate peripherals, and so on. Those features are all pretty routine, though it doesn’t mean they’re easy to implement. Most vendors can claim one or two unique modes that make their chip look like the low-power leader, and the PSoC is no exception. Cypress claims just 22µA/MHz at 3.3V at full speed while using the chip’s internal buck converter, a number that’s a small fraction of what some competing MCUs consume. YMMV.

PSoC 6 devices will come in two basic families: the 62 series, which is geared toward wired interfaces (SPI, USB, et al), and the 63 series, which includes a Bluetooth Low Energy (BLE) link layer and a 2.4-GHz RF transceiver. Apart from those interfaces, 90% of the two families are identical, and both are due to start production in Q4 of this year.

Pricing hasn’t been announced, but the Cypress representatives’ hints and winks suggest something in the low single digits. Figure on about $2.75 to start for a basic device, working up to $5 or $6 for more fully loaded PSoC devices with larger memories, bigger packages, and more peripherals.

Fingerprint detection is one of the extra-cost peripherals that will likely debut within the next year. Some of Cypress’s CapSense technology may be broadly applicable to fingerprint detection, too, making this an easy upgrade for the company.

Speaking of security features, Cypress did. Although it’s tough to gauge the efficacy of any security features, a priori, Cypress seems to have done a thorough job of hacker-proofing the PSoC 6 family. The chips boot up one CPU at a time, with the M0+ waking up first and loading from secure ROM before kick-starting the Cortex-M4 core. That allows the relatively smaller and simpler core to do some internal housekeeping and security checking before the entire chip comes online. Some one-time-programmable key storage and encrypted interfaces should make the chip relatively safe, as these things go.

Another safe choice is the PSoC itself. Cypress has been making these flexible chips for some time now, and they’ve proven popular with developers who need all their features. The programmable analog is unusual (though not unique), as is the touchscreen interface.  The PSoC really does come close to living up to its name. Programming the two ARM cores may be the hardest part of using these components.

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