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Industry Trends: Ecosystems and Packaging

Device Packaging May be Going to the Ball

Two weeks after the three-ring circus that was embedded world (see “Embedded World Diary“), I was at another event: SEMI’s ISS Europe. This was on a different scale and had a different topic. SEMI is the trade body for the companies that build the kit and supply the materials that, in turn, are used to make micro- and nano-electronics. ISS Europe (Industry Strategy Symposium) is a two-day event where members of SEMI are briefed on the trends that are going to shape the industry.

Now some of these trends, particularly the big global socio-economic issues, such as the overall economic climate and the important role of China, were discussed in “May You Live in Interesting Times“.

Other trends included:

The Internet of Things, both as a driver for manufacturing and as a security issue, which included a fascinating presentation on silicon security by Raj Samani of Intel.

The increasing autonomy of cars, where it was interesting to learn that Nissan has set two targets – zero emissions and zero fatalities – for its future cars. For me, the presentation that stole the show was by Solar Team Eindhoven, a student team from the Technical University of Eindhoven, who built a solar-powered four-seat car (rather than a solo racing machine) that won the 2015 World Solar Challenge in Australia. Their website is http://www.solarteameindhoven.nl/, and there is a ton of material on You Tube.

The need for ecosystems for building manufacturing equipment as well as for IP companies like ARM, and the convergence of the ecosystem to a value chain.

FD-SoI as an alternative device-fabrication technology to FinFET. Perhaps this wasn’t surprising, as there were presentations by STMicroelectronics, which was involved in its creation, and GLOBALFOUNDRIES, whose Dresden fab will have it in production.

The topic that really drew my attention and is the real reason for this report was chip packaging. While chips have been following Moore’s Law, the packaging has lagged. But there has been a surge of new activities that are particularly driven by the demands of hand-held and portable devices for smaller and lower-power systems with increased performance. These changes were important parts of the papers from French consultants and analysts Yole Developpement and German research centre Fraunhofer IZM.

Chip packaging has for many years been relatively simple. Bonding wires linked pads on the die surface to a lead frame that was tied to the pins, which served both as electrical connectors and the mechanical method of mounting the die on a printed circuit board (PCB). For expensive chips, the lead frame was part of a ceramic package; for cheaper products, the chip and the lead frame were encased in epoxy. As die got smaller we saw the arrival of the flip-chip. Here solder blobs are deposited on the pads of the chip, the chip is flipped over, and the blobs use a solder reflow technique to attach the chip mechanically and electrically directly onto the pcb, or onto an interposer level, which is then attached to the PCB, usually through a ball grid array (BGA). The chip may again be enclosed in epoxy for protection.

With small chips, it becomes feasible to put two or more different devices in a single package – creating the SiP (System in Package). The advantages include cost (one package is cheaper than two), saving in board real estate – especially for portable devices, and improved performance – signals have to travel only mms rather than cms. SiPs started with the chips sharing the same lead frame using part of the frame to provide communication between the two chips. Later, chips were stacked on top of each other in the first 3D packaging, originally by running wires down the edge of the stacked chips, later with Through Silicon Vias (TSVs) – vertical connections through one chip to connect with the surface of the other. Some 3D approaches use flip chips with interposer layers providing connectivity between them. Again, we are getting smaller packages and improved performance.

But while these approaches are useful, packaging is not keeping up with Moore’s Law. Devices are getting smaller, and it is becoming more difficult to provide links from the chip to the world. This is where we start into the world of Wafer Level Packaging (WLP) and Panel Level Packaging (PLP) and Fan Out.  Wafer level used to mean constructing entire systems on a single wafer, but while there were attempts when wafers were around 4″ in diameter, they never really took off. Today WLP can mean not slicing the wafer into individual die until after making the interconnections, adding the packaging materials, and, usually, carrying out final test and burn-in. This produces an element that is only very slightly bigger than the bare chip.

An alternative approach is to take sliced and “known good” die (KGD) and mount them on a carrier the size and shape of a silicon wafer. Then again, the die are moulded in packaging material and solder balls mounted for the connections. Finally they are removed from the carrier and singulated (sliced up). The advantage of a wafer-level approach is that it can use the established wafer-handling equipment and photo lithography for actions like spreading the mounting and moulding materials and curing them in ovens, and for placing the connectors.

An example of the growth in the use of WLP is the iPhone. According to Fraunhofer, the 1st generation iPhone had 2 WLPs, the 3GS 4, the 4 had 6, the 5 11, the 5S doubled this to 22 and the 6+ has around 26.

PLP is an early-stage emerging technology that takes KGD and puts them into mounting material in a rectangular panel before adding the connections and the moulding material. Where wafer level is limited to the size of a standard 300 mm wafer (with 450 a possibility eventually, but Fraunhofer feels it is not a likely format), PLP is already talking about 18″ by 24″. This would use laser-direct imaging rather than photo lithography, but the tools and processes are still being developed. Even the panel size is a matter for debate.

In both of these processes, there is a need to find a way to link the tiny and closely-packed chip I/O connections to the external world. And that is where fan-out comes in. A technology that has been discussed and tinkered with for many years, it looks about to come into volume production at TSMC with rumours that it will be used for Apple’s next processor.

For wafer-level fan-out, we are looking at placing KGD on a mounting layer. The moulding compound goes on top, then the wafer is flipped and the mounting layer removed. Redistribution lines (RDL) are created, with epoxy acting as insulation between the metals. Typical geometries are 10-micron line-width and spacing.  Solder balls are added to the redistribution lines, and the die are singulated. This produces very low profile packages that are only slightly bigger in area then bare die.

An alternative approach is to create and test the RDLs on the wafer carrier, then place the chips only on those sites that are known good, encapsulate, and singulate.

But one can see that, rather than mounting multiple copies of the same die, you could easily design the RDL to accommodate several different die, creating a new form of SiP. The RDL would be used for communication, both between the chips and with the outside world. There seems to be some serious work on this approach, which has yet to be publicly discussed, but applications for this approach include disease diagnostics, integrated cameras and memory, and communication added to existing products in a 3D package.

Unless you were directly involved, packaging has always been the poor Cinderella, but now it looks as though her fairy godmother has appeared and packaging is getting all dressed up.

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