feature article
Subscribe to EE Journal Daily Newsletter

Altera Turbos the Tools

Spectra-Q Accelerates Quartus II

When people are curious about the performance and capabilities of programmable logic products, they often get buried in the details of the datasheet. It’s easy to get wrapped up in debating LUT counts, Fmax numbers, and a bunch of other silicon-related esoterica that may have little to do with how well a particular device will perform in your application.  

You know what matters a lot more than the details of the chips? The performance of the tools. 

The under-appreciated universal truth of programmable logic is that tools usually have a lot more to do with the success of your design than the silicon does. Luckily, even though the customers don’t always understand this, the vendors certainly do. Altera and Xilinx each spend a substantial share of their engineering budgets developing and improving their tools in order to gain a competitive advantage and make their customers more successful with their devices.

This week, Altera announced the latest volley in the mostly behind-the-scenes battle of the tools with a complete overhaul of the implementation engines (tools like design creation, synthesis, and place-and-route) in their Quartus II tool suite. The new technology is under an umbrella Altera calls “Spectra-Q”.

Spectra-Q is an expansive set of enhancements that work together to improve design turnaround time, design performance, ease of entry and use, and re-use of IP. Starting at the base level, Altera has re-designed and enhanced the core algorithms of their implementation tools for much better performance and quality-of-results. At the same time, they apparently noticed that modern computing environments typically have more than one processor (design tool development folks can be slow to notice these things sometimes), and they have made the tool suite adept at taking advantage of parallel computing resources. The company claims the overall performance improvement is around 8x. In fact, Altera marketing is throwing down – claiming the “fastest compile times in the industry.” We don’t have a way to validate that claim yet, so you’ll all have to let us know.

What we can validate is that the design challenges with the upcoming generation of programmable logic devices are daunting. With millions of LUTs, complex IO, hardened processing subsystems, and applications that demand a complex mix of hardware and software, the “one dude” FPGA design team will be a thing of the past. Design will require copious amounts of IP re-use and the collaboration of teams of both hardware and software engineers. These are the areas where Altera has really made strides with Spectra-Q. 

First, Altera has developed a smooth flow for hardened, drag-and-drop IP use. Once you’ve got an IP block placed and routed and debugged with timing closed, it can be dragged and dropped into subsequent designs as-is. This saves considerable time because the IP blocks don’t have to be recompiled for each re-use. This also means that they don’t have to undergo the often-iterative process of timing closure with each re-use. Once an IP block design is done, it’s done. While this approach may sometimes (in theory) give up a tiny bit of optimization potential, the practical downside is approximately nil. The upside is huge. More of the design nailed down frees up tools, engineers, and compute resources to work on the part of the design that matters.

When it comes to interfaces, you deal with actual physical interfaces rather than manually and individually managing pins and assignments. And this capability is important enough that Altera gave it a name: “BluePrint Platform Designer.” In addition to saving time, this promises to drastically reduce one of the largest sources of careless errors and design tedium. The intelligence in BluePrint understands your interface and will allow it to be dropped only where there is valid IO support on the device. That means that interface and pin-out specification that could literally take days can now be completed in minutes. Altera claims that this intelligent capability reduces iteration on interface specification by 10x. That number probably varies depending on your skill level, but it certainly will have a major impact.

As you might have guessed already, this drag-and-drop-ness of physical IP blocks and interfaces is part of an overall transition to a fully hierarchical design flow. Rather than throwing the entire design up in the air for a lengthy compile each time, your team can work on individual hierarchical blocks, combining and assembling as you go, without having to re-optimize everything with each new run. In real-world design, this could save enormous amounts of engineering time (or non-engineering time, depending how you look at it – you’ll have far fewer opportunities to run to Starbucks while waiting for the tools do their thing).

Perhaps the most intriguing part of Spectra-Q is at the front end. Altera has both unified and diversified their design entry paradigm. Recognizing that the world is made up of more than HDL designers, and that design challenges are not all with datapaths, Altera has built an infrastructure to support multiple languages and design entry flows. Of course, you can still design with RTL, but there are also software-based flows such as the previously released OpenCL flow, a new C/C++ flow called “A++ Compiler for HLS,” and model-based design using popular sources like Matlab and Simulink. Behind all of these flows is a single high-level design compiler (that is reportedly based on the existing OpenCL compiler) that provides the logic implementation and optimization behind all of the current and future high-level design flows. 

Unifying the software flow and beefing up the high-level compilation should have a substantial impact on the task of hardware/software partitioning – which is one of the biggest challenges and advantages of using devices like Altera’s SoC FPGAs. When you have a chip with both FPGA fabric and high-performance conventional processors, you have the opportunity to optimize each part of your algorithm or compute task to take advantage of the best part of the heterogeneous computing environment. If you do that optimization well, the benefits in terms of performance, throughput, latency, and (probably most importantly) power consumption are substantial. Now, Altera has given you a much-improved set of tools to help you take advantage of that opportunity.

Early access to all this new stuff will begin immediately with Quartus II version 15.0. In addition to the Spectra-Q enhancements, the new release contains substantial IP, including Hybrid Memory Cube and HDMI 2.0 MegaCores for the company’s Arria® 10 FPGAs and SoCs and an upgrade in features and device support for the JESD204B core updating Arria V support to 9.255Gbps as well as Cyclone V support up to 5Gbps.

All of this represents a pretty substantial upgrade to Quartus II, just in time for the serious designs that will be going into the company’s upcoming Intel-fabbed 14nm Stratix Generation 10 FPGAs. With Spectra-Q, the prospects of embarking on one of those projects just got a lot less frightening.

4 thoughts on “Altera Turbos the Tools”

  1. Was at a talk by someone trying to get some modeling software running on SMP(X86), GP-GPU, or FPGA, and while the FPGA won on power and speed the compile time was about half a day vs a matter of minutes to run the software, so maybe they’re getting closer to beating the GPUs?

  2. @Kev,
    Don’t hold your breath for FPGA tools to get faster than software compilers – ever. FPGAs will make dramatic improvements in execution speed and particularly power consumption compared with GPUs or conventional processors. But there will always be a substantial penalty in “compile time” because there is so much more going on besides just “compilation”. The first and fastest step of the high-level FPGA implementation flow does basically the same thing as a software compiler. After that, we have logic synthesis, place-and-route, and timing closure. Those steps will not go away and they are extremely computation intensive.

  3. Pingback: GVK Bioscience

Leave a Reply

featured blogs
Sep 18, 2017
A friend of mine was saying the other day, “I want to be able to go to my car, type something like New York City , take a nap, and have the car wake me when I get there.” My friend lives in California; barring supersonic auto 2 [*] transportation, it would be a long...
Sep 15, 2017
Glass Weave Skew. For most people it probably sounds like a progressive rock band. But we’re talking about Glass Weave Skew and differential signals. Brandon Gore, Senior Staff Signal Integrity Engineer, and the Manager of Samtec’s Signal Integrity Group, R&D...
Sep 01, 2017
Achronix was delighted to attend the Hot Chips event in Cupertino once again this August. This year saw a bumper turnout, with some very fascinating speakers providing some great insights into the industry. The Achronix team had a chance to meet with many talented people in t...