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FinFEUD

Blood Battles in FPGA Marketing

He eyed the horizon suspiciously as he leaned his shotgun against the porch railing and reclined into the wooden seat suspended on chains from the rafters. Things had been a bit too quiet lately, and quiet was never good. Those neighbors of his – he chuckled to himself at the irony of calling them “neighbors,” both because they were several miles apart (although on adjoining properties), and because there hadn’t been a kind word spoken between their clans for the best part of three decades – THOSE neighbors of his were up to something, and he aimed to figure out what it was.

A few miles away, in a musty storm shelter lit by a single incandescent bulb, the neighbors were indeed up to something. They had plans for mister porch swing, and he was not going to like them one bit. They couldn’t wait to see the expression on his face when he realized – far too late – what they’d been building down here. Maybe, finally, this would be their year. The year they settled the score. The year that all that pain and suffering would pay off, and those neighbors would get their comeuppance. It was long overdue. 

The grudge match between Xilinx and Altera goes back to a time before some of today’s FPGA customers were even born. Both companies began producing programmable logic devices way back in 1984, and the 29 years since then have seen their share of dastardly deeds done with the sole purpose of upending their archrivals in the FPGA market. Nowhere does this FPGA feud get more heated than when the biennial tick of the Moore’s Law clock rolls us into a new process generation. It is then that each side reveals what they’ve been cooking in the basement for the past several years, and the FPGA community gets its first look at the latest round of weaponry that will be deployed in the never-ending quest for programmable logic supremacy and bragging rights.

The past few rounds of this battle have seen some interesting swings – Altera struck hard at the 40/45nm node – by most accounts besting Xilinx with their TSMC-fabbed Stratix IV and Arria IV families. Altera had brewed up some nice devices – with particularly strong SerDes capabilities, while Xilinx struggled with SerDes issues in their released products. Altera’s results showed it, with design wins and then market share making noticeable gains during those families’ reign.  

Xilinx came back with a vengeance at 28nm – moving from long-time foundry partner UMC to TSMC, which leveled the playing field when it came to FPGA fab choice. Xilinx made two good moves at 28nm. First, they chose the “HPL” (high-performance/low-power) variant of TSMC’s 28nm process – which gave their devices excellent performance-to-power ratios. Altera chose the slightly faster but much more power-hungry “HP” (high-performance) formula. This gave Xilinx more flexibility in the features they could add without running afoul of power budgets. Second, they executed their development process exceptionally well, getting the breadth of their new FPGA families in customer hands well ahead of their long-time rivals. As a result, Altera was on the ropes for much of this round, and they needed to do something significant in order to strike back.

According to conventional wisdom, the next process node should have been 20nm. In fact, both Altera and Xilinx were known to be working on new families of devices based on TSMC’s upcoming 20nm CMOS process. However, at any given time, the big FPGA companies have numerous projects running in parallel. There is usually some lingering work on legacy families that are shipping in production volumes – sometimes including creating additional speed grades, filling out the line with additional device sizes, or rolling out high-rel, rad-hard, market-specific, or special packaging versions of the devices. Then there is work on the most recently announced families/processes getting up to production volumes and yields on all members of the family and fixing any issues found early in the cycle. (Today, this is what is happening with both Altera and Xilinx on the 28nm families.) Next, there is work on the next, still-secret, device families – usually on the upcoming, next-smaller process geometry. Finally, there is always work on the future – at least one process generation beyond. 

So, by the time an FPGA company makes a public announcement about their next family, work has probably been underway on that family for at least one or two years, and there are probably at least one or two years more work remaining before all members of that generation are shipping in volume. Moore’s Law at FPGA companies is therefore at least a three-stage pipeline – and sometimes there are four stages or more. Deciding when to actually announce a new generation of FPGAs, therefore, is a marketing and strategy brinksmanship challenge – as we explained in detail in our 2008 article “45nm Chicken – We Win”. 

Altera apparently felt they needed more of a game-changer than simply proceeding as expected with TSMC’s 20nm planar technology for their next generation. Early in the cycle, industry expectations on 20nm planar CMOS processes in general were low, and experts were not expecting the usual PPC (power, performance, and cost) benefits usually associated with jumping to a new, smaller node. At the same time, Intel was rolling out the first production FinFET (Intel calls them “Tri-Gate” transistors) with impressive results. FinFETs produced better performance at significantly lower power levels than conventional planar transistors. 

So, last fall, Altera announced that they would be working with Intel on a new, FinFET-based, 14nm family. Since Intel is generally about a process node ahead of the rest of the industry, there was immediate and intense speculation on when Altera and Intel would be able to deliver – and how that delivery would line up with the expected TSMC 20nm time line. If Intel was as “ahead” as many believed, and if Altera had already been working with them for awhile before the announcement, Altera might have a 14nm FinFET family ready to go very close to the expected launch date of both companies’ expected TSMC 20nm planar CMOS FPGA families. The advantage of a full process node plus the FinFET advantage could give Altera’s devices something resembling a two-node advantage in performance, power, and cost over their contemporaries. 

This announcement created marketing risk for both companies. For Altera, they now needed to explain their strategy to the world with regard to TSMC and Intel, and they needed to set expectations with their customer base on what would be delivered when. Last month, the company answered a number of those questions when they announced their “Generation 10” Stratix and Arria FPGA families explaining that the next Stratix family would be fabricated based on Intel’s 14nm Tri-Gate (FinFET) process, and the next Arria family would be based on TSMC’s 20nm planar process.

Altera’s new families are not due for a while yet – with Arria 10 scheduled for later in 2013, and with Intel-fabbed Stratix 10 scheduled to get rolling in 2014. This level of disclosure put pressure on Xilinx to show their hand on at least some of their future plans. Otherwise, the market might assume that Xilinx’s next big show would be new families based only on TSMC’s 20nm process – which would give them a clear view of Altera’s tail lights for at least two years. Xilinx responded by announcing what they call “FinFast”, a program to accelerate the schedule of TSMC’s own 16nm FinFET development with Xilinx FPGAs. While it is almost certain that Xilinx was already working with TSMC on 16nm FinFET, the announcement is almost certainly a response to the Altera/Intel disclosure. By simply announcing that they too were in the FinFET race, Xilinx has a chance to freeze Xilinx customers that might be looking over the fence expectantly at Altera’s nice lawn.

Now the FinFET race is on in earnest. Only Altera has announced any details of what we can expect with FinFET FPGAs, but we can assume that Xilinx will not be announcing something both later and weaker. Each side has significant factors in their favor. Altera has Intel’s long-term leadership in production semiconductor processes and the fact that Intel has already produced FinFET-based FPGAs at 22nm with both Tabula and Achronix. On Xilinx’s side of the ledger, they are continuing with long-term partner TSMC who – while they may typically lag Intel in semiconductor technology – has significantly more experience as a merchant foundry than Intel.

Both companies have said they’ll be delivering “in 2014,” so the schedule ramp is likely to be close – with no more than mere months separating the two companies’ releases. However, that will all depend on execution and partnering – between Xilinx/TSMC and Altera/Intel. You can bet that there will be a lot of midnight oil burned in a lot of basements over the next 24 months trying to get some very large and complex FinFET-based FPGAs ready for battle in the market.

Meanwhile, however, there are additional spoilers in the game, and the feud ain’t just the Hatfields and McCoys no more. Both Tabula and Achronix will be shipping high-performance Intel-fabbed, FinFET-based FPGAs long before the traditional market leaders. These interlopers are certain to take at least some market share and to muddy the competitive waters. How the big two companies will respond to these challenges is another piece of the puzzle yet to be seen.

The next 18 months should be a wild ride.

2 thoughts on “FinFEUD”

  1. Do engineers really get so hung up on the latest process numbers? I spend a lot of time working on legacy projects, and the biggest issue for me is having to use ISE! Xilinx have world class FPGAs and 3rd World software.

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