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Grenoble News

An EDA DATE in the French Alps

DATE used to be a smaller version of DAC: a significant trade show with a small conference. Companies took large stands to show off the latest and greatest in EDA, and it was often used to pre-announce news for DAC. It alternated between Paris and Munich, both destination cities.

Today DATE is very different. It has become a deeply technical and mainly academic research-based conference, with a small show attached. It alternates between Dresden in Germany and Grenoble in France.  Why, you might ask, Grenoble? It is not the easiest of places to get to, surrounded as it is by mountains. Its own, small, airport is 25 miles away. But when you start to look at what is happening there, suddenly having a technology conference makes sense.

It is the heart of a global competitive cluster. This is a new piece of jargon for government-supported attempts to recreate the environment of the early days of Silicon Valley. There are a number of these in Europe, supported usually by the European Union, the relevant national government, and often a regional government. (Dresden is at the heart of Silicon Saxony, another cluster.) In Grenoble, the cluster is called Minalogic, and, like all clusters, it has links with a university, the Grenoble Institute of Technology. (There are four other universities in Grenoble, all derived from the original foundation of 1339, with the 60,000 students making up 10% of the city’s population). Supporting the university are research centres, including CEA-Leti, and laboratories for other leading French government-backed organizations, as well as divisions of large companies, including Schneider Electric, STMicroelectronics, NXP Semiconductors, Freescale, CapGemini, France Telecom, Bull, and Atmel. Surrounding these is a host of start-ups and spin-offs, both from the university and from the companies.

Grenoble itself is an area of flat land, at the junction of two rivers surrounded by mountains, and a major winter-sports centre. So a good place for a technology conference.

This year DATE, like so many conferences, had multiple parallel threads, with up to eight sessions running at a time, often with two or three of these looking equally interesting.  As I said, apart from some executive sessions, many of the papers stem from academic work, and the presenters are from around the world, with even mainland China beginning to provide papers. Some sessions can be seen as a reflection of the topics that academia sees as important, or, perhaps just as interesting, topics for research (although they will have had to find someone, somewhere, sufficiently interested to fund their research). What follows is merely a set of snapshots.

One topic that recurred is parallelism. We have already seen that the whole conference is run in parallel, and the EDA tool vendors are stressing that many of the stages of the EDA process are increasingly run on multiple processors. This can be tens to hundreds in the design flow, moving to hundreds to thousands as designs are translated into mask sets. There is also the parallelism of 2.5-D and 3-D devices. And finally there are the issues of implementing and testing multicore devices, which was the topic of a number of the sessions.

A number of the session titles asked questions. For example, one was, “Is reusing off-the-shelf semiconductor IP possible today?” This was a purely industrial panel, with Tensilica (which is in the course of being absorbed by Cadence), Synopsys, whose IP business is a big earner, and ARM. These three companies each have a different position in IP: Tensilica provides customisable cores for offloading tasks from a main processor onto the data plane, Synopsys has a huge portfolio of IP that can be dropped into a design, and ARM, as we know, now dominates the market for processor cores. While there was agreement that the ideal of slotting together IP like Lego blocks was still a dream, there was also agreement that it was possible to reuse “off-the-shelf semiconductor IP,” but only once you had come to a mutual understanding as to what the term actually means.

While virtually each of the sessions I attended would make a full-length article in its own right, my favorite session was one to celebrate the legacy of Mead and Conway. Anyone entering chip design after 1980, and indeed anyone already active in chip design in 1980, had to be aware of the book, Introduction to VLSI Systems, by Carver Mead and Lynn Conway. (Incidentally, if you have a copy in good condition, check out the pricing on the web.) This influenced many hundreds of designers and thousands of designs. It was interesting to see the audience, many of whom were likely to have been already working when the book was published. Alberto Sangiovanni-Vincentelli, another legend in the industry, introduced the session by pointing out that the Mead and Conway approach brought a method and procedure to what had been a fairly ill-disciplined subject. While this legacy is valuable, the other target, the “silicon compiler,” has never, despite an extra-ordinary amount of time and effort, been a commercial success.

Another fun session was on energy harvesting for automotive applications. There are mutiple ways to harvest energy, and a really good automotive one is to exploit thermal differences, since an exhaust system is normally distinctly hotter than the rest of the environment. However, when a car is starting, the exhaust system is at ambient temperature. One of the reasons for looking at energy harvesting is to provide a local power supply for the many different sensors that a vehicle is accumulating. Local power and wireless communication cut down on copper wiring, reducing manufacturing cost and weight and removing points of failure. Other sources for energy harvesting include light, vibration, and piezo-electric, electro-static, and electromagnetic effects, producing power measured in milli- and micro-watts.

Co-operation is increasingly a necessity, and it looks as though moving to ever small geometries will require that all companies along the chain: EDA companies, IP vendors, equipment suppliers and customers will have to work together. A panel, nearly depleted by weather and illness, came to pretty close agreement on this, although again with reservations.

Another panel looked at layered devices – the 2.5D and 3D chips. With 2.5D, a number of different devices are assembled on a carrier layer. This provides density and flexibility. True 3D, with multiple layers of silicon, including layers of memory, processing, and logic, connected by Through Silicon Vias (TSV), is proving more difficult to produce. The panel members, mainly from chip makers, are convinced that the problems will have to resolved, and indeed will be resolved, if we are going to be able to continue to add greater functionality without larger board real-estate.

Counterfeiting, taken broadly to include through re-marking recycled parts, through changing the speed marking of genuine parts, or through over-manufacturing and diverting into grey channels, is an increasing issue, estimated to be coming up to 1% of total semiconductor sales. University research is working at two approaches: encrypted signatures within silicon and making package marking more difficult and expensive. This research, like many of the European academic presentations, was undertaken as part of a programme funded by the European Union. These projects are normally multi-national and involve collaboration with industry – there is more on one aspect of this in my report last December on ARTEMIS (link in here).  The big proviso with this funding of research is that it has to be “pre-competitive” – the end result still has to be turned into a product by someone.

A European project that has recently finished, SYNAPTICS, was the subject of a workshop at DATE. I couldn’t attend it but got a very interesting briefing later from Giuseppe Desoli of STMicroelectronics.  

Using regular patterns on silicon as a way of improving manufacturability in very small geometries has shown a great deal of promise with experimental wafers. But to design circuits that will be efficiently implemented as regular structures, efficient both in the use of silicon real estate and in power consumption, requires a restricted set of design rules that have to be recognised from synthesis onwards. SYNAPTICS (SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms –  snappy title, guys) was set up to explore what this meant for the process flow. The lead company was NanGate, then Danish, now a California-based EDA company. Also participating were STMicroelectronics, Thales (the big defence contractor), Imec (Belgium), Universitat Politècnica de Catalunya – UPC (Spain), Universidade Federal do Rio Grande do Sul – UFRGS (Brazil), Politecnico di Milano – POLIMI (Italy) and Leading Edge – snc (Italy).

Like many real development projects, the outcome was not exactly what was originally envisaged, but there were some very useful results. In particular, synthesis tools that looked at creating cells for use with regular patterns produced, in some cases, dramatic improvements – up to 50% improvement in silicon area, but with considerable effort. While the detailed results are still some way from commercialisation, the project demonstrated that using regular patterning is going to be possible, but there needs to be a lot of work to take the tool flow from the lab to commercial reality.

The event organisers claim that there were 1600 visitors, which seems likely, most of whom came for the papers, of which 55% were from outside Europe. Over 500 papers were delivered, only a half of those submitted for selection. In addition to the papers, there were also poster sessions where researchers, mostly PhD and post-doctoral, talked about work in progress. This meant that many of the people present were young and enthusiastic. The jaded elders were there, but even they were infected by the enthusiasm. How much of what we heard will make it into real tools for EDA is uncertain, but it looks as though there is a strong generation coming up that will continue to push the EDA industry forward, if the existing companies can find a way of channelling this energy.

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