We’ve yammered on a lot in these pages about how these newfangled FPGA whipper-snapper chips are neater’n dirt when it comes to crankin’ out a whole mess-o lickety-split figgerin’ fastern’ you can say “Bob’s yer Uncle.” Yep, if you got something like that whatcha call digital signal processin’, they got them some-o them there DSP blocks that can do yer times-es, your gozeintas, yer take-aways, and yer summin’. You just pile up the data and pump it in, and the FPGA will do the figgerin’ fastern’ cuzin Winki can go through a stack-o flapjacks.

The problem, of course, with “cuzin Winki” eating “flapjacks” is that somebody has to prepare and serve them – and they need to be going at least as fast as “cuzin WInki” can eat. Before an FPGA can really shine on applications like signal processing, you have to be able to gather data (which is probably analog), convert it accurately to the digital domain, and somehow get it into your FPGA at a speed worthy of the FPGA’s considerable computational abilities. Given that the FPGA companies are claiming that the latest generation of FPGAs can crunch data somewhere in the realm of teraFLOPs, that means you have to provide data at a remarkable rate.

Analog Devices is well known for their fast and accurate analog-to-digital converters (ADCs). Their converters are often used in high-performance applications like medical imaging, ultrasound, military and aerospace imaging, and industrial imaging. These ADCs have impressive specs and can generate data at remarkable rates. For example, the company has just announced a dual, 14-bit, 250-megasample-per-second (MSPS) ADC – aimed at just the types of applications we are discussing. If you do a little math on those specs, you’ll realize that our kitchen is cookin’ up the flapjacks plenty fast, and the problem is getting them from there to the table. 

FPGA companies have long recognized that you need big, fast pipes to get data into and out of FPGAs as fast as the devices can process it. That’s why we’ve been talking about multi-gigabit serial interfaces (SerDes) for several years now. The big problem has been that most ADCs are not wired up with high-speed serial interfaces, so the FPGAs and the ADCs don’t speak any common language that takes advantage of the bandwidth that SerDes can provide.

Luckily, a few years ago, JEDEC saw this problem and introduced a series of standards allowing devices like ADCs to connect to SerDes interfaces on devices like FPGAs. The first version – JESD204 2006 – provided for 3.125 Gbps SerDes interfaces to data converters. The second version of the standard – JESD204A 2008 – added support for multiple data lanes and lane synchronization. Now, a third version – JESD204B – has arrived with three new major enhancements: A higher maximum lane rate (up to 12.5 Gbps per channel), support for deterministic latency, and support for harmonic frame clocking.

Analog Devices has moved quickly to release devices on this new standard, and they have just announced the AD9250 dual, 14-bit, 250MSPS ADC supporting the JESD204B standard. These devices achieve 70.6dBfs signal-to-noise ratio at 185MHz Ain, and 88dBc SFDR at 185MHz Ain. They support a flexible input range from 1.4Vp-p to 2Vp-p with an analog input bandwidth of up to 400MHz. They are fairly power thrifty – given the fact that they’re pushing SerDes interfaces – at 711mW total power at 250Msps (both channels). The devices are powered by a 1.8V analog power supply, and they have an on-chip internal voltage reference. 

These new ADCs can be configured as (L=2, S=1, F=2, M=2) – 1 data lane per ADC up to 250MSPS resulting in 5Gbps data rate, or as (L=1, S=1, F=4, M=2) – shared data lane up to 125Msps resulting in 5Gbps data rate. This means you can combine SerDes lanes to support super-fast transfer from one ADC, or you can multiplex a single fast data lane to share output from multiple, slower ADCs. This flexibility allows a greater range of applications to take advantage of SerDes connectivity for data converters, bringing the advantages of simpler board layout, vastly reduced IO pin usage, higher data rates, and more robust design. 

The AD9250 devices are available now, and they will be a boon to anyone designing FPGA-based systems for applications like ultrasound. The new JEDEC standard takes full advantage of the latest devices from companies like Xilinx and Altera – with their latest-generation SerDes interfaces and their incredible DSP speed and efficiency.

What if you want to use one or try one out? 

The company says that evaluation platforms are available now, and there is an optional FMC interposer card that will allow you to connect the evaluation board to a Xilinx FPGA board. The company supports the evaluation platforms with “Circuits from the Lab” (proven clocking and ADC driver signal paths), behavior models for ADIsim and IBIS, and web-based design wizards including PLL, filter, op-amp, and clocking solutions. The company also offers a rich set of converter-centric application notes on topics like clocking, input networks, jitter effects, and testing methodologies.

Obviously, Analog Devices is not stopping here with support for JEDEC JESD204B. We expect the company to continue rolling out converters that support the standard, probably in the order of importance of the increased capability to the application areas they support. That means cousin Winky won’t be getting the flapjack version any time soon, unfortunately. However, we think he’ll be just fine with the traditional kitchen-to-table connection for now.