feature article
Subscribe to EE Journal Daily Newsletter

Oil and Water

Taking Advantage of Natural Segregation

Two years ago, a curious technology that had been under academic study for about 20 years for applications having nothing to do with semiconductors was presented in a paper at SPIE Litho as a way to push lithography. The next year there were 74 papers on it, and it was inescapable at this year’s SPIE Litho.

That technology is “directed self-assembly” (DSA). And it’s a complete departure from all of the other lithographic ideas that have been bouncing around as we wait for a) the demise of 193-nm immersion lithography and b) EUV to be ready for production. Although, in reality, it doesn’t really matter what specific lithography is used: it simply leverages what you have through frequency multiplication, much as double-patterning does. In fact, there are aspects of this that harken not only to multi-patterning, but also to some of the more organic tendencies of carbon nanotubes as well as the 1-D line-cutting use of complementary e-beam lithography.

I got a chance to discuss this in more detail with imec’s Kurt Ronse. The basic idea is rooted in the fact that there are organic compounds that will not mix, experiencing natural “phase separation.” Given a mixture applied in a thin film on a surface, these so-called “block co-polymers” will spontaneously unmix; there is a natural “periodicity” or size of “clump” that occurs. The result tends to look something like a fingerprint – random swirls and curves and such, created by alternating parallel arcs of the two polymers. This tendency for the mix to develop such patterns is referred to as self-assembly, since all you have to do is apply the material and it takes care of creating the structure.

Of course, done simply this way, the structure isn’t deterministic or repeatable (assuming an ultra-pure neutral surface underlying the polymers). And the patterns have the kind of organic shape that doesn’t immediately suggest any use in building circuits. Fortunately, the system is amenable to suggestion.

If you bias the material to set up in a straight line, then you end up with a row of parallel lines, with the two co-polymers alternating. The trick is how to bias it – and it’s actually not that hard (in theory).

The most “obvious” way is a process referred to as “grapho-epitaxy,” where you build two straight guiding walls out of some material. The spacing matters: if you put these two walls, say, 80 nm apart, and if your co-polymer naturally separates into 10-nm lines (making up numbers here), then you’ll get eight parallel lines of alternating material (four pairs of lines) between the two guiding walls.

Bear in mind, however, that every other line is a different material, and if all you do is cover wafer with this stuff, well, it doesn’t really do much. But if you selectively etch one of the co-polymers, then you have lines of the remaining co-polymer with spaces in between – this effectively becomes a new spacer technology. And, while you originally had eight 10-nm-wide lines, you’re now left with four line/space pairs with a 20-nm pitch. In other words, by exposing an 80-nm pitch, you end up with a 20-nm pitch, or a multiplication of four. All without using multiple exposures or masks and with no coloring issues.

This is the “directed” in DSA; it takes the otherwise pretty, swirly patterns and turns them into not-so-pretty, but useful, parallel lines.

If you space the guiding walls out further, then, in theory, you get more lines between them. But you can’t push it too far – if the guides are too far apart, then, in the middle area farthest from either side, you can get more of the random stuff that’s not so useful. So you have to pattern the wafer with the guides close together enough to ensure that all the lines will go straight.

The obvious downside of this approach is the fact that you have to use valuable silicon area for these guides – the useful area exists only between the guides; the area covered by the guides is lost.

But there’s an alternative: instead of directing from the sides with a wall, you can bias from underneath using what’s called “electro-chemical affinity.” This process is referred to as “chemo-epitaxy.” You stripe the wafer with lines of this material much as you did the guide walls, but the spaces between those lines are filled to level everything out, and then the copolymer blend is deposited over the whole thing, lines and all. One of the co-polymers selectively “binds” to those lines as the mix self-segregates. It’s as if you had a magnetic line underneath and one of the polymers had iron in it. So, even though you’re laying down guides, because the material self-assembles above it instead of next to it, you don’t end up losing that area.

The natural spacing (10 nm in the hypothetical example) is determined by the polymer length, which becomes a critical materials parameter. In fact, controlling this is one of the challenges of making this technology manufacturable. Mr. Ronse mentioned an experience they had using material that provided 12.5-nm lines. When they ran out of that bottle, the replacement bottle of what was ostensibly the same material self-assembled into 17-nm lines.

Even just getting the purity right is important. When they were first trying this out in a real fab rather than a university lab, the fab managers took one look at the goop – which, in particular, had trace amounts of lithium in it – and wouldn’t let it anywhere near their area. Any metal can create contamination that can be ruinous to the chips being built.

On the other hand, there’s a certain level of forgiveness to the technology. For example, when laying down the guides, if there’s a defect that creates a “hole” in what should be a set of continuous parallel lines, the co-polymers may actually self-assemble correctly anyway – it’s almost as if there’s a kind of momentum that allows small gaps to be crossed without defect. Obviously, if that hole gets too big, then the copolymers may lose their way as they cross the chasm.

The parallel-line configuration, of course, suggests 1-D gridded design approaches, where lines are cut at various key points to define structures that are more useful than parallel lines. But lines aren’t the only possibility: point dots can be used to define contact holes, and, in fact, Mr. Ronse thinks this may be one of the first commercial applications of the technology, one to two years out. The size of the holes is determined by the polymer length, and the holes can be made very uniform – which could be a boon to EUV technology, which, according to Mr. Ronse, exhibits high critical dimension (CD) variation.

Imec has already implemented a full process in a clean room using a flow based on work done at the University of Wisconsin, which uses polystyrene (PS) and poly(methyl methacrylate) (PMMA) (aka – believe it or not – Lucite or Plexiglas) as the two block co-polymers. (PMMA is more familiar in our world as a photo-resist for nano-scale imaging.) They’re still working on reducing defects and improving repeatability.

In particular, they are refining the lithographic sensitivity, the required guide placement accuracy, temperature, line-edge roughness, and the overall chemistry. To check their work, they take a picture of the finished lines and then take a Fourier transform to make sure that the frequency is correct.

Imec is not the only company working on this technology; IBM tends to mention it a lot as well (they said at the Common Platform Alliance that they’re using a multiplier of 4). Exactly when it will be ready for full deployment will probably depend on whom you ask. But this is clearly down the pike a ways – 14 nm or below. So, while you should expect to hear much more about it, don’t expect to start using it in the near future.

2 thoughts on “Oil and Water”

  1. DSA is a promising technoloby but is not mature for applications in the LEDs and PSS patterning business, let alone ICs. The main issue is that there is no way (as far as I know) of patterning complex ICs with DSA and the variability of the dimensions is still way too high.

    At Nanotech Japan a few months ago, I spoke with the CEO of a company working with nanoimprint. HE explored DSA but found out that the same results you could get with DSA were basically achievable by simply etching a large substrate that would also crate similar structures.

Leave a Reply

featured blogs
Oct 23, 2017
In the comments to blog #5, Frank Wiedmann asked about the correlation between the results of mismatch from Monte Carlo analysis and DC mismatch analysis. It is a fair question and here is a short blog to explore the topic. The example may not be realistic, but it is a useful...
Oct 19, 2017
Choosing the right plating is critical to the success of a connector system. Plating affects the connector’s performance, life cycle, quality, and cost. A recent blog explains that pins and plating are usually the main cost drivers in board-to-board connector systems. T...
Oct 19, 2017
The annual Hot Chips conference in Silicon Valley offers a reliable window into the architectural thinking of both CPU giants and exciting start-ups. This year proved to be no exception, as architects squared off against the limitations of physics and the demands of workloads...
Sep 29, 2017
Our existing customers ask us some pretty big questions: “How can this technology implement a step-change in my specific process? How can Speedcore IP be integrated in my SoC? How can you increase the performance of my ASIC?” We revel in answering such questions. Ho...