feature article
Subscribe Now

The MEMS Testing Quagmire

Players are Increasingly Looking for Extrication

Testing is an unfortunate but important requirement for being in the chip business. Unfortunate because it’s expensive and, well, annoying. Important because no one would trust electronics that had never been tested. And systems builders would end up throwing a lot of useless stuff away. It’s the “failure costs 10x as much for each later stage at which it’s caught” thing.

When we test standard digital ICs, we have two places to catch problems. At the wafer level, we can probe and run some tests to ensure that we package up only devices that look promising. We can’t guarantee that chips tested at the wafer level will be good, partly because the testing involves long probes that aren’t good for things like performance tests, but also because continued processing as the chips get put into packages can introduce new defects.

So we have to do further “final” testing at the packaged part level to be sure that what goes out the door is good. And we might do some occasional sampling for things that we’ve decided not to test – because we thought they’d be fine – just to make sure that they are indeed fine.

Testing costs money, of course, so lots of effort goes into figuring out how to test as little as possible and, for what remains, how to test it as quickly as possible.

Testing analog chips gets a bit more difficult simply because the parameters that define success vary much more wildly than they do with digital chips. So exactly what you have to test and how you accomplish that test can differ dramatically between devices. High-precision parameters might be slower to test due to long settling times. Still, it can usually be done with electrical connections at the device and, to some extent, at the wafer level.

But let’s take things one step further: MEMS. Now it really get tricky. You’re not testing electrical phenomena; you’re testing the electrical response to mechanical phenomena. Much different.

Add to that the historical mindset of MEMS players, perhaps as articulated through the bill of a seagull: “Mine… mine… mine…” MEMS manufacturing in general varies all over the map depending on what kind of gizmo you’re building. You have to tailor the materials and processing steps on a device-by-device basis. Yole, who appear to be the predominant analysts tracking MEMS, have what has been called the Yole MEMS Law: “One product, one process, one package.” Some have proposed adding, “and one test” to that list.

As a result, there’s been little, if any, cooperation between players. Each has acted the lone wolf, doggedly handling everything on their own. They learned the hard way how to build and package and test their devices; no way they were going to share that with anyone else. “You want a piece of this? You can start from scratch just like we did.”

But here’s the deal: this is starting to get painful for everyone. When you break down the cost of building a MEMS device, the test component of that ranges typically from 20-50% of the entire cost of the unit – one outlier has test chewing up 80% of the total cost.

Even when combining MEMS and CMOS, where 80% of the processing is shared, only 20% of the tests are shared. The MEMS portion is simply a different game. And the use of foundries and other subcontracting is becoming more common now. Each handoff between entities requires testing to make sure everything is OK. So everyone is coming around to the idea that some level of cooperation may benefit all.

To address the growing concern, the MEMS Industry Group (MIG), along with the National Institute of Standards and Technology (NIST), did a series of questionnaires and workshops to figure out what to do. Notably, NIST being a piece of the US Department of Commerce, it was a US-centric study in some regards, with US competitiveness being part of the motivators for action.

The bottom-line outcome of the study was that we need to do something: standards would be good. And they came away agreeing that there are “pre-competitive” points where collaboration makes sense.

Now you might think the obvious thing is to follow the model set out by IC manufacturers; we do build MEMS devices on wafers, after all. But it’s actually not that simple. With ICs, the measurements you do at wafer sort may not be completely accurate, but they’re a good predictor of which devices will turn out to be good. So wafer sort is an important step of the IC flow.

But what about an accelerometer? You need to move the unit to test it. Now, back in the day, when I was an engineer wandering amongst the test machines (engineers are suspect on the production floor on the best of days; it only gets worse from there), I might have bumped into a tester that was in process on a wafer. I don’t recall specifically doing that, but it suits my general lurching gait, and, whether it was for that or for some other reason, I definitely know the glare that such a bump would earn from whoever is managing the floor at the time.

Let’s just say that putting probes on a wafer and then shaking it to test the response… not such a good plan. And lots of MEMS devices run afoul of this issue simply because of the second M in MEMS: mechanical. It boils down to the fact that you can really only do electrical tests efficiently on a wafer, and electrical tests aren’t much good at predicting which MEMS units will be good after packaging.

So, as a result, they’re going to address wafer testing, but it’s not a sure bet. The higher priority is to focus on standards for packaged device testing. There’s plenty to be done there. Implications range from which tests are done to how they’re done to how the parameters are specified on their datasheets. They will also be distinguishing between qualification tests (what you do to make sure your product is ready to release) and production tests (what you do for each manufactured unit or on a sampling basis).

Right now it’s only a plan to do something; we don’t have results yet. We’ll keep our eyes open to see what comes of the process.

 

More info:

MEMS Testing Standards Report

9 thoughts on “The MEMS Testing Quagmire”

  1. Pingback: bandar judi
  2. Pingback: agen bola online
  3. Pingback: agen poker terbaik
  4. Pingback: training your dog
  5. Pingback: Coehumanl

Leave a Reply

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...