One thing was crystal clear in last week’s Embedded Systems Conference in San Jose.  FPGAs with embedded processors are about to take over the world.

Now, we don’t really mean the WHOLE world here – just the part of it that involves flexible embedded processing systems, of course.  Still, if you look at embedded systems in use today, you’ll usually find some kind of programmable logic device sitting next to the processor.  FPGA companies – being what they are – looked at all those boards and thought to themselves, “Hey, we could just slurp that processor right onto our FPGA!” 

So Altera did just that… in 2001… as part of their “SOPC” strategy.  It was called “Excalibur,” and it failed miserably.

For the next ten years, however, Altera was not failing at embedded systems with FPGAs.  With their Nios and Nios II soft-core processors, and their SOPC Builder software, they defined the category of systems-on-programmable-chips by making FPGA-based SoC designs both easy and fun.  I mean, “fun” if you enjoy that sort of thing.

Of course there was competition.  Across town, archrival Xilinx had their own embedded soft-core processor – MicroBlaze, and their own software for stitching together embedded designs with just a few keystrokes.  Altera kept the heat turned up on embedded design with FPGAs, however. 

Now, the stakes have gotten higher.  Xilinx has recently announced Zynq, an embedded computing platform featuring ARM A9 processors, copious peripherals, and FPGA fabric – all on one chip.  Altera is expected to announce a similar platform very soon.  While the details of the architecture of these two new-category chips will be analyzed at length over the coming months, we already have interesting details on the software and structures that will be used to design them.

As part of their Quartus II version 11.0 release this week, Altera is announcing the production version of their new Qsys embedded design tool.  Qsys will be the cockpit for assembling high-performance embedded systems on Altera FPGAs, and it will also be the place to go for selecting and stitching together IP blocks on your Altera FPGA design.  Qsys will replace the venerable SOPC Builder tool – with bigger, better, faster, and easier technology. 

When the first version of the old SOPC Builder tool was released, users were invited to take the new idea for a spin.  In just minutes, the company claimed, you could stitch together all you needed in an embedded system – processor, memory, busses, and peripherals.  I took the challenge and was quite pleasantly surprised to learn that even an editor could create a simple processing platform – capable of executing the landmark “Hello World” executable – in just a few minutes, with no assistance whatsoever.  My system had probably five or six components, total.  

Over the next ten years, however, users’ demands on that system increased.  People wanted more performance on their interconnect, more flexibility in the user interface, and the ability to create hierarchy in their designs.  One FAE, according to the company, took a printout of a complex embedded system design that used over 150 components, and stood on a stool holding the paper over his head.  It extended all the way to the floor.  This photo became a rallying point for the team developing Qsys, and the results show in the tool.  Customers with larger, 50+ and 80+ component designs must be able to handle them with ease.  The tool must operate hierarchically, and any design must be able to be a component in a higher-level design.

Qsys picks up where SOPC Builder left off, and it goes many places where the old tool could not.  At the heart of the new product is a network-on-chip that will be the standard for IP interconnect for Altera going forward.  End applications are demanding higher performance – with standards such as PCIe and 10G Ethernet.  To meet those needs, a faster interconnect was needed – that would also be compatible with older designs.  Altera’s NoC is a packet-based network.  Packets as wide as 64-128 bits can be efficiently routed from source to destination. 

As an example of the higher performance of the new NoC, Altera just released a reference design that does PCI Express Gen 2 x4 to DDR3 – with up to 1400MB/sec throughput.  That kind of performance is well beyond the capabilities of SOPC Builder’s interconnect.  The new NoC allows us to make the tradeoff between throughput, latency, and resources in a meaningful way.  For each connection, you can dial-in the amount of pipelining you want – from zero to four stages.  More pipelining delivers more significantly more performance – at a cost of some resources and latency.  

Since Qsys is Altera’s IP assembly tool, we asked how much re-work of existing IP was necessary to be able to use legacy blocks with Qsys and with the new NoC.  The simple answer is “none.”  Legacy IP will work just fine in the new environment.  However, since SOPC Builder offered zero pipelining, and the Qsys NoC offers up to four levels, people supplying performance-critical IP blocks may well choose to re-work them to take advantage of the new performance opportunities.  Altera themselves are doing this with blocks such as PCI Express.

Unlike the previous interconnect fabric, Altera has made this new NoC “hackable.”  If you don’t like the way your stuff is hooked up, you can go in and manually change it around to meet your goals.  While we believe most people won’t actually end up taking advantage of this feature, many will be glad the capability is there. 

Since Altera is planning to release an ARM-based hard-core processing platform on their own FPGAs soon, we asked about support for AXI.  Altera explained that, since the NoC transaction layer is separate from the transport layer, it is easy for them to support other protocols such as AXI.  The company says AXI support will be available later this year.  For developers of IP that is intended to be cross-platform, from ASIC implementations to multiple FPGA vendors, this convergence of interconnect is one less headache to worry about.

Although SOPC Builder was designed as a general-purpose IP connection tool, it clearly had a bias toward Altera’s Nios family processors.  The new Qsys tool, however, was designed from the ground up with the reality of multiple processing alternatives and multi-processor designs.  Altera has announced or is actively selling solutions with Nios, ARM, MIPS, and other popular processor architectures.  Qsys should be up to handling all these and more. 

Qsys is designed to help out on the debug and verification side of design as well.  Qsys has a verification IP suite that helps monitor system activity and that can interact via a “system console” to allow your PC to communicate with your design running on your device.  The capability takes the same concept as SignalTap – Altera’s embedded logic analyzer – and extends it to the bus/transaction level.  IP vendors can also take advantage of this capability to instrument their IP for test and debug.

Version 11.0 of Quartus II has a lot of other improvements over its predecessors, of course.  The external memory interface toolkit is improved with the added ability to do performance/efficiency monitoring.  You can use this capability to tweak memory controllers or data to optimize the efficiency of external memories.  Numerous other bug fixes and performance enhancements are mentioned in the notes. 

With Qsys, Altera has moved to a new generation of design tools for embedded design with FPGAs.  We think that this will be one of the most active battlegrounds over the next few years – not just between the various FPGA companies, but between FPGA companies and suppliers of traditional embedded processing platforms.  In fact, we may soon see a day when Altera and Xilinx spend more energy positioning against companies like Freescale and NXP than against each other. 

Nah, that’ll never happen.