feature article
Subscribe Now

An Offer of Surrender

The West is not known for its capacity for nuance. Especially in the US, we excel at black-and-white thinking. You’re either with us or against us.

And we’re competitive. The goal is to win. And there’s only one alternative to winning: losing. And losing is for losers.

If you’re going to lose, it’s best to lose the good fight: surrender is weakness. Better to die fighting than live a loser. (Easy for the winners to say…)

But “surrender” has another related, but more subtle, meaning: release, submission, acceptance. The serenity to accept things that can’t be changed. The “surrender” to which the Arabic word “???????” (“al-islam”) translates. The belligerent “Surrender, Dorothy!” becomes the well-intentioned, “Dude, chillax!”

Surrender is also about letting go of control. And, while that process may eventually bring peace (assuming things go well), it’s a bit of an emotional arc getting there: it starts with a surge of anxiety as the death-grip is relaxed and control is ceded to some other entity (living, spiritual, or inanimate).

And it is this arc upon which analog designers have an opportunity to embark. Because, of all the engineering denizens upon which automation has been visited, none is more storied in its resistance than the analog designer. And, while those stories may impart some humor at the expense of him-of-the-most-awesomely-long-beard, the chuckles mingle with a goodly measure of admiration and respect.

Because we know they’re right. Most likely, they can do a better job than some new-fangled machine. They’re our modern John Henrys. They get to hand-craft their results, not just so that it works right, but even so that it looks right, aesthetics bolstering confidence that all is well. They practice a craft and an art, firmly rooted in science.

So there have been no analog synthesis tools. Layout contains much hand work. And, what tools have been brought in to assist these guys are solely that: helpers, under the firm supervision of the designer.

Digital designers have long ago given themselves over to the massive tools that can spray out transistors in quantities that mere mortals could never manage. While automatic, these tools can still be influenced by designers, and a big part of that comes from the use of constraints. But a good many of those constraints specify a result: a speed or power limit, for example, that must be attained. It’s not so much controlling the tool as it is telling the tool what you want and letting the tool go off and do whatever it needs to do to achieve the result. Having to take more control than that indicates a broken digital process: the tool wasn’t able to deliver the desired result.

So when you hear that Cadence is now making formal constraints available for analog designers, you might perk up your ears and wonder if synthesis tools are on the way for analog. And the answer is: no, not really.

Analog circuits have their own specific requirements that have to be met, and the relevant parameters will vary widely depending on the function. It might be bandwidth; it might be signal-to-noise ratio; it might be gain. It’s not a simple speed/power/area world.

In fact, the constraints that Cadence is providing are lower-level, having their origin in simple notes between designer and layout engineer. Up to now, if a designer needed two transistors to be matched, he or she would make a note on the schematic, and the layout engineer would proceed accordingly. He wouldn’t tell the layout engineer that he wanted a particular gain: it’s his job as a designer to figure out how to achieve the gain. So he would still do the design work, annotating those bits of the design that rely on the layout engineer for success.

What’s new is the formalization of these “notes” as constraints that can be understood both by layout tools and by simulation. Using the matching example, you can specify that two transistors be matched, but not specify the size. Then you can play with the size in simulation to decide which to use; the matching constraint will apply that size to both transistors and ensure that you don’t forget to keep them the same.

There are quite a few constraints that can be summoned up. The placement constraint menu alone allows you to specify symmetry, matching, absolute orientation, relative orientation (“I don’t care what direction, but they should both be the same”), alignment, spacing, clusters and cluster boundaries, correlation, IR drop, and the broad category of “modgen,” which is essentially a layout wizard that can automate common placement patterns.

There’s also a “circuit prospector”: it can look at the design, identify common patterns, and add default constraints that can be reviewed, modified, and over-ridden as necessary.

Constraints can still be used for communication between design and layout, and permissions can be set up to allow either or both sides to update some or all of the constraints and have them annotated (or back-annotated) on the schematics and layout.

Both the schematic and layout views allow you to look at a list of the constraints and their status. Hopefully a green check mark will indicate that the constraint has been met; you will also see if some haven’t been met or aren’t feasible. Coloring on the schematic and layout can be used to help you visualize which elements belong to a given constraint – two matched transistors will have the same color, for example.

As you embark on your quest of surrender, you can take things one step at a time. Initially, you can specify the constraint, implement it manually, and let a checker confirm whether or not the constraint was met. Those ready to take the plunge can let the tools actually implement the constraints (actually, a subset of the constraints: not all can drive the tools); the checker can still confirm whether or not your trust was well placed.

So, after all the fuss and worry over whether to let the tools take over, this surrender is nominal: you’re just giving the tools some space to work. You can rely on them to help drive design quality, but it’s still under your close supervision. The dog has gotten a longer leash, but it’s still on a leash.

In fact, perhaps it’s the best of both worlds: you can experience surrender and still remain in charge.

Leave a Reply

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...