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Modeling the Power Minutiae of your Chip

Think of it as scaling down a smart meter.

We used to characterize the power into our homes with one number per month. OK, two: the kWH and the price. One might stay the same month to month, the other goes up.

For reasons of power optimization – managing and reducing the amount of power we take off the grid – we are moving into the smart meter world. (Well, except for a few areas around here where they’ve instituted moratoria due to the purported falling of the sky.) Now we can characterize – even model – our power usage with much finer granularity and precision.

Too much, some would say… One ISSCC paper this year discussed identifying various pieces of equipment in use based on the power signature (not just on/off events, but actually running). And there’s a rumor (I have no idea if it’s true) that Google is in line to buy the power usage information from the power companies so that they can see exactly what each of us is doing when. (You know, if they’re doing that, why don’t they just give up the pretense and install Google RoomView, with a live GoogleCam (no opt-outs) in every room so that anyone can virtually enter your abode and watch what’s going on… And Google can inventory your belongings to see what you’re missing, including a FridgeView that shows what food you’re out of, so they can send unblockable ads to your Android phone that will interrupt anything you’re doing… but I digress…)

So power optimization and power modeling go hand in hand here. And it can be rather complex too, depending on how complicated the household is. Newborn baby, with nighttime feedings? Frequent travel, with no one home? Busy teenagers coming and going at all hours? Crackhouse? Each of these use models comes with different modes. Newborn-baby model has short-sleep mode, groggy feeding mode, and then barely-awake daytime mode. Frequent travel model has home mode and away mode. Crackhouse model has guest-at-the-door mode, idle mode, and (when the cops show up) scatter/gather mode.

Now… let’s scale this waaaaayyyy down (think “Honey, I Shrunk the Grid”), where we’re not monitoring the power to our house, but to a chip under design. (Modeling a chip that’s already live and running poses some similar security concerns, but that’s not the focus for now.) Developing a model of the chip’s power grid helps to confirm that the power remains in budget under a variety of circumstances, that there are no bizarre behaviors when clocks start churning and modes start swapping, and that no one has secretly designed a grow operation into one of the modules.

Originally, the power pin would be modeled as current source in parallel with a cap. Estimate the cap, and you’re done. One number says it all, just like the monthly power bill.

But that’s no longer sufficient. Between intentional and parasitic elements, there are billions of devices to model. This is what Apache’s CPM power modeling tool tackles. It takes the design and derives from it a complex power model that is still far simpler than the real chip. Rather than billions of elements, we’re talking hundreds or thousands of SPICE devices. It includes a static aspect, a frequency (RLC) aspect, and a time-domain aspect. How they generate the model is proprietary; they try to balance accuracy and simplicity, targeting results that come within 5-10% of actual silicon measurements.

Part of their overall power integrity offering, this tool has been available for about three years. A few weeks ago they announced version 2.0. The new version adds three capabilities: modes, regulators, and access to internal nodes.

There are several types of mode that can be analyzed. The most obvious are user-defined modes of operation; reset mode, incoming call mode, American Idol video mode (with optional silencing), paperweight mode (also known as unscheduled-reboot mode – what, you think this mode happens by accident?). You can define and name these, bundling all of the results into a single model (rather than a model per mode).

More complex is the ability to analyze the circuit both in “constant power” mode, where the power supply is on and stable, and “variable power” mode, reflecting what may be significant power shifts as the circuit transitions from one mode to another. This allows analysis of the power grid under such transient conditions.

Also within their “modes” category, they now provide resonance-aware characterization. The grid is analyzed for its full frequency response, but then a “carrier” or “ripple” can be added at a specified range to model the response and see whether any of the transistors gets seasick.

Regulators (specifically, low drop-out, or LDO regulators) are elements that they could not previously accommodate in the analysis; a short was assumed in place of the regulator. Such regulators, increasingly common as the number of non-integer power domains increases, can now be included in the model.

Finally, they’ve added visibility of internal nodes. You can assign external ports to these nodes, providing access by various analysis tools. This can help you figure out what’s happening at specific critical parts of the circuit, or at various places in the package.

Put together, the models should be able to reflect much more realistically the complexity of the chips being analyzed as you take them through the increasing number of use cases that have to be covered.

Just like a miniature smart meter. Without the death (or headaches or rashes) by wireless. Without Gladys Kravitz peering through the power signature to see what’s happening after you twitch your nose; no listening to frantic cries of, “Abner!” when she figures it out. No scruffy-looking dude with a glint in his teeth figuring out when you’re away on vacation. No over-eager drug store noticing when you turn your light on at 3 AM, sending you an immediate phone ad for Ambien. And, best of all, no power bill at the end of the month.

More info: Apache CPM

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