feature article
Subscribe Now

Fun With Family Planning

Altera Details 28nm FPGA and ASIC Families

Altera has just released specifics on their upcoming 28nm families, with a data dump that would make Wikileaks proud.  At the highest level, there will be four families of devices – three FPGA families and one ASIC (HardCopy) family.  The three FPGA families differ in their features, density, and performance, and they target different classes of end applications.  The HardCopy V ASIC family offers a cost reduction path and the potential for improving performance and power consumption for Stratix V customers that are headed to higher volumes.

At the high end, we have the already-announced Stratix V FPGA family.  Stratix V is a logical successor to the previous Stratix families, with much higher density, more features, better performance, and lower power consumption.  In other words, all of the things we’d normally expect from a family that has jumped to a new process generation. 

In the mid-range, we have Arria V, which brings substantial density and transceiver performance at a lower price point than Stratix V – for designs that don’t require the bleeding-edge features (like 28Gbps SerDes transceivers).  Arria (which is apparently pronounced \?är-?-?\ like an aria in an opera) comes with very capable SerDes transceivers – in 6Gbps and 10Gbps flavors, up to 495K logic elements, up to 2278 18×18 multipliers, and up to 23,800Kb of memory.  By comparison, the current Stratix IV family offers almost identical memory and transceivers and only half as many 18×18 multipliers, and only one Stratix IV device offers significantly more logic fabric.  It’s fair to say that Arria V would be very competitive with Stratix IV.

Filling out the ranks of Altera’s new 28nm families will be the cost-optimized Cyclone V.  Much like archrival Xilinx, Altera sneaked past a process node with their low-cost offering – with their Cyclone IV family based on older 65nm process technology rather than 40/45nm.  Now, we’re set for a low-cost death match as both Xilinx and Altera bring 28nm low-cost families to market – and those families will be competing with niche low-cost offerings from other vendors.  

According to Altera’s preliminary data sheets, the new Cyclone V will be an enormous leap from current low-cost families.  With up to 300K logic elements, (equivalent 4-input LUTs), up to 12Mb of block RAM, up to 385 DSP blocks, multi-gigabit serial transceivers, and hardened PCIe blocks and memory controllers – a Cyclone V device could give a Stratix III device from just a couple years ago a run for it’s money.  Actually, if it’s about money – Cyclone V would smoke Stratix III hands-down. 

Rounding out the four new families is Altera’s HardCopy ASIC family – which is essentially a service that converts your Stratix V FPGA into an ASIC.  HardCopy has been a popular program for years now, and HardCopy V should be the most robust version yet.  In past incarnations, one of HardCopy’s limitations was lack of SerDes support.  With HardCopy V, that limitation is now lifted, although the fastest (28Gbps) transceivers will still not be available.

Speaking of transceivers – for the first time, every Altera family will be transceiver-equipped.  The company will have it’s broadest portfolio of transceivers ever – with five base transceiver modules at 3G, 5G, 10G, 14G, and 28G.  Starting at the top, the new Stratix V GT boasts four transceivers operating at a mind-boggling 28 Gbps, plus a decent helping of 14 Gbps units (32).  We actually saw an early demonstration of this technology last year.  One notch down, Stratix GX will have up to 66 of the 14 Gbps transceivers.  Moving on down the line, Stratix V GS will have fewer of the 14G units, and Stratix V E brings no transceivers at all to the party – maxing out core logic instead for applications like ASIC prototyping.  

Arria V  GT will be endowed with up to six 10 Gbps transceivers and up to 24 6 Gbps, and Arria V GX is available with up to 36  at 6 Gbps.  Cyclone will be available in E, GX, and GT variants – with up to 12 transceivers at 3Gbps plus hard PCIe and memory controllers. 

Full preliminary product tables for Altera’s newly-announced families are below:

table1.png

Table 1. Preliminary Cyclone V Family Plan


table2.png

Table 2. Preliminary Arria V Family Plan

 

table3.png

Table 3. Preliminary Stratix V GX/GT Family Plans

 

table4.png

Table 4. Preliminary Stratix V GS/E Family Plans

 

The really exciting aspect of this announcement, of course, is how it clears up the battle lines between Altera and archrival Xilinx.  For their 28nm offering, Xilinx is now using the same semiconductor fab Altera has been using all along – TSMC.  One might jump to the conclusion that the two companies’ products will become less differentiated as a result. 

One would be dead wrong.

Starting at the top, with the move to TSMC, Xilinx chose to go through a grand unification of some sort – moving all families to the same process and the same basic logic cell architecture.  Altera, on the other hand, chose to split their lines into two separate processes, optimizing for the goals of each family. 

TSMC actually offers three different processes at 28nm: LP, HP, and HPL.  LP (low power) uses Silicon oxynitride (SiON) and was the first 28nm process to come up at TSMC.  Altera is using this LP process for their Cyclone V and Arria V FPGAs.  The LP process is designed for very low leakage, so it’s great for applications with a requirement for low static power.  The HP (high-performance) process uses high-k metal gate technology.  Altera is using the HP process for their Stratix V FPGAs as well as HardCopy V ASICs.  TSMC’s third process – HPL – is a bit of a middle ground between the two.  HPL is designed for low power with high-k metal gates.  It sacrifices some flat-out speed for lower leakage.  

So – even though Xilinx and Altera are both using TSMC 28nm, it appears that they will have no process in common.  On the schedule front – 28HPL, the process Xilinx is using, is last on TSMC’s production schedule – leading to the speculation that Altera may be able to ramp to volume production earlier.  Further spicing up the story – Xilinx has announced that they will be building some of their high-end devices using a stacked-silicon approach where multiple slices are placed on an interposer layer to create a larger chip.  It seems possible that these slices could be heterogeneous with different processes for things like core logic and high-speed transceivers.

On top of all that – Altera offers their unique “HardCopy” ASIC conversion for customers wanting lower cost and potentially higher performance with less power consumption.  Xilinx’s closest corresponding offering is EasyPath – which offers lower cost for custom-tested FPGAs (which may not be field re-programmable).  Each of these cost-reduction strategies makes different compromises to get the desired result – Altera’s downside being NRE, conversion time, and a less-than-100% mapping of the FPGA part to the ASIC part.  Xilinx’s downside is probably higher cost at volume and no gain in performance or power consumption. 

As if these differences aren’t enough – two new serious threats to the high-end FPGA business have emerged on the scene.  As we announced last year, Achronix has struck a deal with Intel to create super-fast asychronous FPGAs based on Intel’s flagship 22nm process technology.  These devices should be entering the competitive arena only a few months after Altera and Xilinx launch.  In addition, Tabula is making inroads with their time-multiplexed “3D” FPGAs – which offer very high effective density on smaller die – resulting in a big chip for less money. 

With all this competition forming, Altera needs to be loaded for bear – and with these family announcements, it appears they are doing just that.  The range from the smallest Cyclone to the biggest-fastest Stratix V or HardCopy V device will give Altera a huge and varied range of capability to bring to the myriad markets currently adopting programmable logic.

9 thoughts on “Fun With Family Planning”

  1. Pingback: GVK BIO
  2. Pingback: DMPK
  3. Pingback: You Jizz
  4. Pingback: orospu

Leave a Reply

featured blogs
Apr 24, 2018
In mid-April I was at the Linley Processor Conference. As usual, Linley Gwennap gave the opening keynote. He titled it How Well Does Your Processor Support AI? which was the perfect straight man question for us since we were using the conference to announce our new processor,...
Apr 19, 2018
COBO, Silicon Photonics Kevin Burt, Application Engineer at the Samtec Optical Group, walks us through a demonstration using silicon photonics and the COBO (Consortium of Onboard Optics) form factor.  This was displayed at OFC 2018 in San Diego, California. Samtec is a fable...