Altera® timing models provide a simple and easy way to verify the timing of FPGA designs without the need to perform full physical electrical extractions and simulations. The three different operating corners available for 65-nm and newer FPGAs provide a thorough coverage of the time delays within the recommended operating conditions.

Introduction

How can a designer accurately predict the time delays of a fully customizable integrated circuit? The answer to this question is “not very easily.” There are many factors that limit and increase the complexity of accurately modeling time delays in an integrated circuit. A few of these factors include, but are not limited to large space of valid operating conditions (voltage, temperature, process, etc.), complex physical phenomena with (often) non-linear and complicated models, and variability of mass-produced silicon. Altera has devised a method to accurately predict the time delays for all designs implemented in its FPGAs.

To accurately model time delays within an FPGA, Altera uses a combination of two tools: a static timing analysis tool in Altera’s Quartus® II development software called TimeQuest Timing Analyzer and a proprietary circuit simulator with a delay databasefor each FPGA. The simulator combined with the delay database (containing the time delays) are also simply known as timing models. Timing models play a critical part in the FPGA design flow because they are used throughout the FPGA design compilation, from synthesis, through place-and-route, to timing simulation and analysis. This white paper provides an overview of the creation of timing models and the importance of timing models in Altera’s FPGA design flow.

Timing Model Components and Characteristics

Each FPGA has its own unique timing model that contains of all the necessary delay information for all physical elements in the device, such as the combinational adaptive logic modules, memory blocks, interconnects, and registers. The delays encompass all valid combinations of operating conditions for the target FPGA. Also, each element can contain different delay information depending upon the mode or configuration the element is configured to. Essentially, timing models are a software-based representation of the physical delays in the FPGA. To maximize model accuracy and minimize run time, the model is divided into two methods of producing the delay information: the delay database and the proprietary circuit simulator.

Delay Database

The first method of supplying timing models to other Quartus II optimization and analysis engines is the delay database. This database is mostly used to store the delay arcs of logic and hard IP blocks on the FPGA fabric, which are mainly parts of the FPGA architecture that have limited configurability. The delay database accounts for all possible configurations of these blocks as well as any differences in performance and delay between blocks that are functionally identical but have different physical implementation on the chip (i.e., different layout). The main advantage of this method is the low look-up time for delays, which translates into a short run time for the TimeQuest Timing Analyzer.

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