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Laws of Physics and Free Markets Will Create Premium on Power Management Across IC Design

Not long ago, IC design engineers gave scarcely a thought to power-related issues. When it came to the cost-benefit analyses of various features on a chip, power was deemed to be more or less free and unlimited. The number of gates, in contrast, was often the expensive crux of the entire design project.

Now the situation is reversed. Thanks to Moore’s Law, gates are all but free while the cost of power – or more specifically, managing things like dynamic power and leakage – is soaring. In fact power could soon be the overarching challenge in IC (and SoC) design for several reasons.

One is related to the laws of physics. Leakage, or static power, is the energy loss that occurs even when there is no activity on the chip. At 90-nanometer (nm) and smaller manufacturing process nodes, leakage has joined dynamic power consumption, the energy used to switch transistors off and on, as a power management concern. And at the 65-nm technology node, static leakage can constitute as much as 50 percent of total power expenditures [1, 2, 3]. (Intel’s newest Westmere family of processors – much discussed at the 2010 Consumer Electronics Show – incorporate 32-nm technology.)  

Other design drivers relate to the laws and whims of human society, which, though tougher to quantify, are arguably equally as powerful in shaping new products and markets. Consider the raft of environment-related government and social initiatives that aim to mitigate global warming by harnessing the latest developments in energy efficient designs of both portable and non-portable electronic systems. The best example is almost certainly the Energy Star standard for energy efficient consumer products, which has been adopted by the United States, Australia, Canada, Japan, New Zealand, Taiwan and the European Union.

Then, of course, there’s the undeniable demand and cultural cachet for high performance battery-powered mobile devices. Apple’s iPad launch landed Steve Jobs on the cover of the venerable Economist. The world’s preeminent business magazine blared the headline “The Book of Jobs” and displayed the Apple CEO as a down-from-the-mountain Moses, complete with a halo, robes and, of course, carrying a new iPad in lieu of a stone tablet. The analysis from the normally staid Economist: “Jobs’s record suggests that when he blesses a market, it takes off. And tablet computing promises to transform not just one industry, but three—computing, telecoms and media.”

Whether motivated by market hype or solving engineering headaches, if you’re involved in IC design, chances are that, in the months and years ahead, you’ll become increasingly well versed in power-management issues. What follows is my attempt to sketch out the broad outlines of the new design considerations, from circuitry to software to standards.

Change starts at the SoC itself (where else?)

Power gating (with or without state retention), multi-switching (multi-Vt) threshold transistors and multi-supply multi-voltage (MSMV) are among the most effective techniques for static power reduction in SoC designs [2]. The use of any of these active power management techniques impacts the entire development cycle, including the design, implementation and verification of a typical SoC design.

Active power management requires additional circuitry that will reduce or completely switch off supply voltages (VDD and VSS) and bias supplies in certain portions of an SoC at specific stages of its operation. It requires additional power management cells, including special retention registers. Isolation and level shifter cells are also needed to ensure proper operation of the entire SoC when portions of the device are operating at different supply voltage levels or have their supply voltage turned off while the rest of the device remains operational.

Accordingly, nearly any attempt to incorporate power management features introduces additional design states and functionality that must be verified. Among the typical verification concerns:

  • behavior of blocks that are turned “ON” must not be compromised when other portions of the design are turned “OFF” or placed in standby mode
  • where different parts of the device are operating at different supply voltages, adequate protection circuitry should be inserted to provide electrical and logical isolation and to prevent excessive currents that could lead to thermal runaway and, ultimately, a breakdown of the device
  • a power domain that is turned “OFF” must be able to be turned “ON” and resume operation; this may require retention of critical state information or a reset upon powering “ON” or a combination of the two
  • standby, power-up and power-down protocols must be properly followed
  • the system must be able to enter, transition among and operate correctly in all power modes that it supports

The limits of software and simulation

Beyond the new circuitry, software is key to building and creating power-aware devices. Examples include the operating system functions that monitor key parameters, including temperature and system loading, and embedded software applications that determine when certain power domains should be shut down based on the function currently being performed. Power-management requirements invariably introduce a new layer of complexity in hardware-software interactions, which now must be verified to ensure proper operation of the device in all of its supported power modes.

Together, these hardware and software issues introduce a significant amount of schedule risk, largely due to the additional work that the verification engineer has to perform on top of the already enormous task of verifying the SoC’s core functions. And these issues are new, since, until recently, design and verification of low-power designs employing active power management circuitry were done using ad hoc techniques at the gate level or later in the SoC design process.

Unfortunately, given today’s design sizes, verification at the gate level would be too slow and come too late. It’s also exceedingly difficult to debug at this level given the lack of correlation between the RTL (that verification engineers are familiar with) and the gate-level netlist. The net effect is an increased risk of RTL errors escaping to the manufactured device.

Adding power management functionality directly into RTL designs in order to verify it early in the process creates additional issues. First, it limits opportunities for reuse since the power architecture is now fixed in the design. Second, any changes to the power architecture now require verification of both the logic functionality and the embedded power management circuitry.

There is also the issue that VHDL and Verilog, the primary languages for describing digital designs at the RTL and gate levels, abstract away the notion of power supplies..

A new standard to the rescue

If you care about power-management in IC design, then have a look at the Wikipedia page for IEEE Standard 1801-2009. The standard, known as Unified Power Format (UPF) 2.0, is arguably the worldwide engineering community’s most significant attempt yet to pave the way for new power-aware devices. UPF, first developed by Accellera, is currently supported by multiple vendors and is in use worldwide. The March 19, 2009 announcement about the approval of IEEE 1801 marked the first time that UPF has undergone an IEEE standardization effort. 

UPF makes it possible to describe the low power architecture of an SoC in a file separate from the design description in RTL. The UPF description includes:

  • an abstract description of the power supplies, switches and the power distribution network for the SoC
  • a description of the power domains of the SoC and identification of the RTL instances that belong in each power domain
  • a specification of low-power strategies for retention, isolation and level shifting
  • power state tables that define the different power states of the power domains of the SoC

The low power architecture described in UPF becomes the common view seen by implementation and verification tools at any given level of abstraction. In addition, the UPF standard defines semantics that are common for both verification and implementation tools that support UPF. These semantics extend the traditional HDL semantics to include the notion of voltage, power domain and power states.

20100511_mentorFig1.jpg

Fig 1: The UPF side file provides a consistent semantic for all tools throughout the design and verification flow

In a UPF-enabled verification methodology, the following tasks can be easily performed:

  • comprehensive and automated clock domain crossing verification of the RTL, independent of the power architecture that verifies correct clock domain synchronization, including verifying protocol adherence and reconvergence
  • power-aware simulation that leverages the low-power architecture described using the UPF standard, including hardware software co-verification
  • power-aware equivalence checking tools that check golden RTL + UPF against gate-level netlist + UPF, which ensures that implementation tools honor the low-power architecture specified in the UPF description

A UPF-based verification flow allows for early verification of the low-power architecture at RTL, where it is easier to find and fix power management issues in the design. UPF annotation also benefits verification tools, especially those that are able to leverage the information contained in the UPF format to apply power-aware simulation semantics. Among such information: corruption of logic values in a power domain that is in the “OFF” state and inference of power management behavior such as isolation and retention.

Other verification improvements include automated debugging of common power management issues in the design, generation of coverage information based on UPF content and improved RTL IP reuse in different low-power contexts. This last benefit is made possible because the low-power architecture is contained in a separate file. 

20110511_mentorFig2.jpg

Figure 2: Diagram showing a typical power-managed design, including design elements and the power management artifacts that are inferred from a UPF file (see inset image at top) by a power-aware simulation tool.

A quick note here before moving on to synthesis: since power management is a system-level concern, software components often form part of the power management solution. When this is the case, it’s necessary to verify the software and hardware components of the power management solution within the same debug environment using hardware/software co-verification tools. In this sort of common debugging framework, the software and hardware states are synchronized with each other and presented in a way that greatly improves debug productivity of tough-to-find bugs at hardware/software interfaces.

Once the design (in RTL) and the low power architecture (in UPF) have been fully verified, implementation tools such as synthesis can be used to transform the design into a technology-dependent gate-level representation. It is important to verify that the low-power intent captured in the UPF is preserved during this process. Using logic equivalency tools that are power- and UPF-aware, this verification task can be performed easily.

Power-aware logic equivalency tools ensure that verified RTL + UPF is equivalent to the implemented gate-level netlist + UPF output from implementation tools. In addition to checking for logic equivalency, these tools also ensure that power management strategies such as isolation, retention and level-shifting are preserved throughout the implementation steps.

I’m an EDA guy so of course I think that tools are critical. But so is the ability to take in the big picture. So here’s my attempt to conclude doing just that:

Power management techniques create new design and verification challenges across the scope of a project. This means that, if you don’t already possess one, it’s time to develop a working vocabulary of the active power management design techniques that can reduce the total power consumption of an IC design: clock gating, power gating (or power shutoff), MSMV, and so on.

After learning the basics of these techniques and beginning to introduce them into your design, it’s critical to ensure that the design is still functionally correct as early as possible in the design process, typically at the RTL level, and always prior to implementation. And, throughout the successive implementation steps in the design process, always ensure that the functionality of your design is maintained when power management features are added.

Doing all this won’t change the fact that power is an increasingly critical design consideration. Remember those immutable laws of physics and fast changing markets. It will, however begin to lay the groundwork for the new skills and experience necessary to thrive in an environment where power management is an increasingly ubiquitous requirement for just about any IC-based device.

References:

1.      J. Kao, S. Narendra, and A. Chandrakasan. ”Subthreshold leakage modeling and reduction techniques”. In IEEE International Conference on Computer-Aided Design, pages 141–148, 2002.

2.      G.Chidolue and B. Ramanadin. “Upping Verification Productivity of Low Power Designs” Proceedings of the San Jose Design and Verification Conference, DVCon, pages 3-10, 2008.

3.      P. McCrorie “On-Chip Thermal Analysis Is Becoming Mandatory” http://chipdesignmag.com/display.php?articleId=2171&issueId=27

About the author:

Gabe Chidolue is a Mentor Graphics verification technologist in the U.K. (Newbury). Write to him at gabriel_chidolue@mentor.com

 

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