If there is a hierarchy of techie-ness, analog designers come pretty high-up in the hierarchy. Where digital IC design teams have moved from drawing polygons, through schematic entry to RTL, and are now grappling with ESL tools, the analog guys continue to draw polygons. And analog design is hard: it takes a long time to learn to do, and it requires a special mind-set to do it well. This has always been a problem, and it is becoming an even more serious problem as analog moves from being a niche activity to something that, if not centre stage, is certainly playing a major supporting role in many devices. Where analog used to be confined to its own chip, SoCs and ASICs are adding areas of analog and mixed signal for greatly increased functionality.
The lack of tools is a problem not only at the layout stage. Compared to the digital world, there are very few tools for simulation, verification and layout and even fewer examples of a complete development tool chain. While some tools do exist, different flavours of SPICE for modelling, for example, they are often difficult to calibrate, complex to use and, despite vendors’ claims, not always as accurate as their digital counterparts. The consequences of a mistake made when implementing a basic element may not emerge until the silicon is under test: by that time the mistake can be difficult to identify and very expensive to fix.
The manufacturing processes for analog circuits have traditionally lagged the digital state-of–the-art. Now analog processes are entering the sub-micron world, and this is making analog design even more difficult. The same process issues that are plaguing digital design are even more of an issue for analog circuits, and, in particular, process variations and parasitic effects are having significant effect on the end products.
Of course there have been many attempts to develop tools for analog. But so far there have not been many great successes. Today the consensus is that most of the analog design tools available are expensive (even by the already high standards of digital EDA tools), inadequate, or require significant changes in working practices. And some manage to combine all three problems.
Tanner EDA is not claiming to have cracked the big problem. A small 20-year-old company specialising in analog and mixed signal design, Tanner has a number of low-cost tools for different stages of the design cycle. (The company was reviewed last year – see article here). Now the company is introducing a new tool, licensed from Ireland-based design services company, IC Mask Design, that automates the basic, even, one might say, the drudgery aspects of design capture, to free designers to use their skill in the higher levels of the design. HiPer DevGen (which Tanner claims means High Performance Device Generator) generates the primitives that are the basic elements of analog design. These include such things as current mirrors, differential pairs, and resistor dividers, as well as transistors and resistors.
Working with DevGen, the designer first selects the manufacturing process technology. (Tanner has loaded data from many of the major foundries’ process design kits (PDKs), and this data is available as part of the maintenance contract.) Then the designer selects a primitive and, from drop down menus, chooses the appropriate electrical characteristics. Pressing the right button lets DevGen use its knowledge of the manufacturing design rules and of the electrical constraints, such as matching requirements, to generate the basic building blocks. The designers then use their hard-won skills to connect the blocks together to make an effective overall design.
While there are basic default values for the primitives, these can all be modified to meet the specific requirements of the design. An example that Tanner provides is that DevGen will normally try to optimise drain parasitics over source parasitics in a differential pair. However, when source capacitance is important, in circuits such as down mixers for example, the designer can change the parameters, regenerate the differential pair and then simulate to see how this works. Since generating the new differential pair takes only seconds, this cycle can be repeated until the design converges to an optimal solution.
Tanner’s marketing material contains a number of examples of different circuits, but the most extreme that is discussed starts with a schematic of 17 functional devices. A poll of engineers produced estimates of between two hours and two days to create the circuit. The elements were created “instantaneously” by a layout engineer using DevGen. An extra ten dummy devices, needed to ensure balancing, were also automatically created.
But while this is good headline stuff, the real advantage comes when you need to make a change. Today this will typically require significant effort and time, perhaps needing as much work as creating the original design. Tanner reckons that changes are also close to “instantaneous” (presumably after you have spent time resetting the parameters that you entered before the initial instantaneous generation).
The tool was initially produced by a company that actually does analog design for real projects and, as such, it has been designed to complement the designers’ skills, not replace them. In some ways it is the equivalent of the old days of design when an engineer threw a schematic at a draughtsman, who drew the polygons by hand on drafting film. Now DevGen is replacing the fallible draughtsman with a knowledgeable software package.
More about HiPer DevGen can be found at http://www.tannereda.com/devgenoffering – which has links to video demos and an extensive white paper.
I was introduced to HiPer DevGen at DATE, the European EDA tools conference, held this year in Dresden. At the same event OSCI (Open SystemC Initiative) launched the SystemC Analog/Mixed-signal (AMS) extensions language standard, AMS 1.0. To quote the release, “The AMS 1.0 standard is the first modeling language targeting system-level design and verification to describe analog/mixed-signal behavior as natural extension to existing SystemC-based design methodologies.” With AMS 1.0 you can begin to define AMS modelling tools that will inter-operate with digital SystemC tools to define future complex SoCs and ASICs. These tools don’t exist at the moment, and some commentators feel that, despite the definitions within AMS 1.0, it will be a long time before the mainstream EDA vendors produce tools that will be acceptable to analog designers.
Discussions with SoC and ASIC designers, plus data from the foundries, make it clear that the analog portions of a design are likely to continue to be significant bottlenecks in future product development. The way to remove that bottleneck is new tools, yet there is a general feeling that these tools are a long way away. Looks to me as though it is a good time to be an analog designer. (Or maybe it is a good time to work on producing new tools?)
