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Taming Thin Film

Tier Logic's Approach to 3D FPGAs

Apparently, having an old 2D FPGA on your development board will soon be as lame as having one of those old-school 2D flatscreen TVs on your wall.  Sure, 2D FPGAs are good, but the buzz is all about 3D these days.  If it hasn’t got a Z axis, we easily-distracted trade press editors may not see it sticking up past all the other bright, shiny objects.

The latest entry in the 3D derby comes from startup Tier Logic, who have come out of stealth mode to give us a new spin on what 3-dimensional programmable devices may look like. According to Tier Logic, that third dimension is built from thin film (apparently, it’s a “thin” third dimension).  The company claims that innovative process changes allow them to remove the configuration SRAM (a huge chunk of a conventional SRAM FPGA) from the normal die and put it upstairs on a new level built with thin film technology.  The FPGA uses the normal nine layers of metal characteristic of current semiconductor processes, then adds thin film (TFT) layers on top of that, implementing the configuration logic.  

This is an elegant solution to an architectural oddity that has plagued FPGAs from the beginning. With conventional SRAM FPGAs, most of the transistors on the device are used for configuration logic.  Those transistors don’t need to be fast.  They need to be stable and not leak.  However, as we make our processes smaller and faster, these transistors become leakier and present a significant challenge for keeping static power down on FPGAs.  

One of the reasons thin film transistors haven’t caught on much in logic design is that the transistors are comparatively slow.  Since the steps to add the thin film to the top of the regular layers can’t be done at more than 400 degrees C, the silicon is amorphous.  Amorphous transistors are normally a bad deal but, fortuitously, are very well suited for FPGA configuration. They sit there on top of the stack, sipping power and holding your configuration.  

Having the configuration pulled out of the fray makes the whole FPGA more efficient from a layout perspective.  Routing distances are smaller, leakage currents are lower, timing closure is less challenging (in theory, at least) – all the benefits you’d expect from a 3D IC come true.  Tier Logic claims a net gain of 1.8x to 3.5x over conventional FPGAs.  

That 1.8x to 3.5x gain translates very roughly into 1-2 process nodes.  If that’s true, from a pure FPGA device technology perspective, Tier Logic just has to be within one process node of the “big guys” to be competitive on a cost, power, and performance basis.

Tier Logic has their sights set on more than that, however.  

You see, if you skip the thin film (TFT) layers, and put metal up there instead, you’ve just created a metal-wired ASIC version of your FPGA design.  The ASIC version is cheaper, faster, and lower power.  You can prototype your design, do early production, and get the kinks worked out by doing all your iteration and revision on the FPGA version, then when you’re ready to go for volume cost savings – get the metal-programmed version and you’ve just shortcutted the dreaded ASIC design process.

This is a process very similar to Altera’s HardCopy ASIC.  However since the device was designed from the ground up with the dual-mode TFT/metal configuration in mind, we expect that the final ASIC version might be more densely packed than Altera’s process of replacing SRAM configuration with metal.  Time, datasheets, and production runs will tell.

Tier Logic is tackling the NRE challenge as well.  They claim that the NRE for your FPGA-to-ASIC conversion is less than $50K, and turnaround time within four weeks.  They are running an initial promotion that aims to bring people over from competitive FPGAs.  That program waives the NRE and conversion costs for production orders of $100K or more and takes your existing FPGA design from another vendor – delivering you TierASIC samples (which can be made pin-compatible to your existing FPGA).  The company says they are ready to take orders for the ASIC version today with production in Q2 2010, and they expect to sample the TierFPGA devices in Q2 with production in Q4.

This one-two punch of FPGA and ASIC is a fantastic way to evolve your product and to reduce or mitigate the risk that comes with designing an ASIC right from the start.  It provides the technical foundation for a nimble business strategy – evolving your product fast to keep differentiation while having an easy, low-engineering path to cost reduction for margin improvement.

So, how do we design one of these things?

The tool flow for TierFPGA is happily just what we’d expect.  Normal, HDL design flow with simulation, synthesis, and place-and-route all behaving as one would expect.  For synthesis, Tier Logic has partnered with Mentor Graphics for their Precision synthesis tool.  The same flow can be used for both TierFPGA and TierASIC.  Or, as we mentioned before, an existing Xilinx or Altera design can be submitted directly to Tier Logic for ASIC conversion.

What does all this mean?

We are seeing a continuing wave of startups touting major architectural innovation in the FPGA space – Achronix with asynchronous devices, SiliconBlue with innovative cost- and power-saving features and NVM architecture, Tabula with time-multiplexed 3D FPGA fabric, and now Tier Logic with TFT-based 3D FPGAs and matching ASICs.  Each of these innovations offers something like a 1-2 process generation advantage over conventional architectures.  Xilinx and Altera continue with a more evolutionary, incremental improvement strategy – reliant mainly upon reaching the next process node first to stay ahead of the competition. 

Whether one or more of these innovations will be the “magic bullet” that catapults a startup into major market share has yet to be seen.  However, the pace of innovation is impressive, and whether one or more of these ideas becomes a major differentiator on its own, or is acquired or consolidated into another line – we as consumers of FPGAs will benefit. 

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