feature article
Subscribe Now

It’s Just Cool

Is Smart Fusion an FPGA? Who Cares?

In a world of increasing integration, applying past labels often becomes a pointless side-trip through downtown futility.

That iPhone in your pocket – is it a phone? Well, it has “Phone” in the name. Is it a portable computer? A digital camera? A GPS? A pager? A media player?

We can spend hours debating the semantics of various ill-fitting labels when trying to describe a new integrated device. It really doesn’t pay. The best thing to do is to just try to decide whether the things we’ve integrated together make sense and work well as a unit. The iPhone combination listed above is proven to work pretty well. If somebody comes out with a combination electric-shaver/taser, we’ll be less enthusiastic. Something is a little off-putting about getting up in the morning and having to be careful not to press the wrong button…

So, we won’t worry about whether Actel’s newly introduced SmartFusion is an FPGA or a microcontroller or a programmable analog device. It just doesn’t matter. The important question is whether the combination is well executed and useful.

SmartFusion is the sequel to Actel’s novel and successful Fusion line. Fusion combined FPGA fabric with programmable analog to give us a great little low-power progammable platform for applications like motor control and power management. Usually, however, we wanted to add a microcontroller to that equation to smarten up our design a bit. With the old Fusion, Actel gave us the option to add a soft-core microcontroller (ARM’s Cortex M1) to handle the control aspect of these designs. This approach had a couple of limitations, however. First, the MCU took up a big chunk of our FPGA fabric, leaving us with limited room to add custom hardware and peripherals. Second, the soft-core version of the MCU didn’t have nearly the performance we’d expect from an optimized core such as the M1’s big brother – the Cortex M3.

With SmartFusion, Actel has solved both of these problems. The new family includes an optimized 100MHz Cortex M3 right on the chip. In addition to running faster and using less power than the soft-core M1, the hardened processor uses less silicon area and leaves more FPGA fabric available for more custom logic. Actel has bolstered the memory up to 64K-512K of flash and 16K-64K of SRAM, so the processor has some decent resources to play with without having to go off chip. While they were at it, Actel also hardened most of the common peripherals people will be wanting with their M3. They added a pair of UARTs, a DMA controller, RTC, I2C, SPI, and even a 10/100 Ethernet MAC. As Jim Turley pointed out in his Embedded Technology Journal article last week – these are most of the things you’d expect to find in a typical $5 Cortex-based microcontroller.

If you had a typical $5 Cortex-based microcontroller, however, you’d probably then be asking for an FPGA to go with it. You’d need the FPGA fabric to add a couple of missing peripherals – maybe more UARTS, some other custom logic – and to manage the connectivity to some other part of your design. In your overall design, then – you need to add the cost of that FPGA, the extra board real-estate, the extra power from running two devices and the associated I/O, and so forth. Then, if your application hooks to anything non-digital, you’ll need some analog mixed in there as well – with another round of associated costs and design complexity.

With SmartFusion, all that stuff comes packaged in the original chip. SmartFusion appears to have less FPGA fabric than the older Fusion family, but don’t let the datasheet dupe you. With the Cortex M3 and all those peripherals already hardened and waiting on the chip, the amount of fabric you have left for custom logic is way more than Fusion offered. With SmartFusion, your design is likely to be cheaper, faster, and lower power than the same project done with the older technology. If you’re coming from a discrete MCU, FPGA, and analog solution, it will be all those, plus it will be smaller and more reliable. SmartFusion is available in some very small packages, and by skipping all the board design required to hook up separate components, you dramatically reduce potential points of failure.

Actel has been following their own path in the FPGA market for a long time now. They have augmented their dominant position in rad-hard antifuse FPGAs with a strong lineup of low-power flash-based devices like their ProASIC and Igloo families. In each case, they weren’t going head-to-head with the larger SRAM FPGA vendors, but instead focusing on more specialized applications that aren’t well served by mainstream FPGAs. With SmartFusion, however, they are really aiming outside of the FPGA market altogether. Instead of seeing competitors like Xilinx, Altera, and Lattice, they’ll be bumping heads with the likes of TI’s Luminary Micro, Renesas, and NXP. The biggest difference being that their competitors’ catalogs will have dozens to hundreds of devices with different combinations of peripherals and accessories, and Actel’s catalog will have just a few options for SmartFusion devices that you can customize with exactly the peripherals and accessories you need. 

Even though we’re not worried about calling them FPGAs, SmartFusion devices have a generous helping of flash-based FPGA goodness. The family ranges from 60,000 to 500,000 “system gates” of logic fabric (no, we still don’t know what a “system gate” is either) with up to 350MHz performance (as usual, your mileage may vary) and up to 204 user IOs. Because this is flash-based fabric, there is no need to reconfigure the FPGA at each power-up, and you can build your system as a single-chip solution if you so desire.

In addition to the FPGA fabric and the Cortex M3 and peripherals (which we’ve already discussed), SmartFusion boasts a programmable analog section called the Analog Compute Engine (ACE). The ACE performs sample sequencing and computation – offloading the M3 from analog initialization and processing. The analog portion itself includes up to three 12-bit ADCs with 600 KHz sampling rate, and up to three 12-bit first order sigma-delta DACs – all with 1% accuracy. The analog goodies also include up to ten 50ns comparators and a number of temperature, voltage, and current monitors.

The design flow is supported by Actel’s Libero development suite, and the software development support includes a full, Eclipse-based IDE (along with all your favorite ARM-friendly development tools, of course). Unlike the typical newly-announced FPGA family, SmartFusion devices are available now. Yep, that means right now and in production volume. The A2F200 is available immediately, and it will be followed by the A2F500 in Q2 and the A2F060 in the second half of the year. Evaluation kits are $99 and the full-blown development kit goes for $999.

Leave a Reply

featured blogs
Aug 15, 2018
https://youtu.be/6a0znbVfFJk \ Coming from the Cadence parking lot (camera Sean) Monday: Jobs: Farmer, Baker Tuesday: Jobs: Printer, Chocolate Maker Wednesday: Jobs: Programmer, Caver Thursday: Jobs: Some Lessons Learned Friday: Jobs: Five Lessons www.breakfastbytes.com Sign ...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 15, 2018
The world recognizes the American healthcare system for its innovation in precision medicine, surgical techniques, medical devices, and drug development. But they'€™ve been slow to adopt 21st century t...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...