It’s that time again.
The process calendar has struck two, Gordon Moore’s little hand is pointing to the 28nm, and his big hand is pointing to sometime later this year. The usual competitors are strapped into their seats. They’ve donned their rhetoric helmets, engaged their marketing drives, and shifted their gearboxes into “disclose”.
Instead of re-publishing our popular “45nm Chicken” article with 45 scratched out and 28 written in in crayon, we’ll just give you a link so you can read it again now. It won’t take long, and it’ll help you understand what’s going on with Xilinx and Altera the past few weeks in the biennial process node rollout rat race. (Go read it)
Done? OK. Since there are just two primary competitors in the FPGA node wars at this point (not to diminish the importance of Lattice, Actel, SiliconBlue, Achronix, Tabula and others – they just aren’t in the “who can seem like they’re first on the new process node” battle), the contest is a lot more of a match race than a sprint. Instead of just running full speed toward the finish line, the two competitors base each move on the other’s last move – sometimes drafting in the slipstream, and sometimes covering to stay between the other competitor and the finish line.
Xilinx gave us a glimpse this week into what they’ll be doing in 28nm – giving up the “who announces first?” position in exchange for announcing with the other team’s cards in plain view.
Starting with the choice of fab partner, the big news is that Xilinx will be using TSMC and Samsung for 28nm.
Why is this big news?
Because Xilinx and Altera have historically been deadlocked in a marketing standoff regarding their fab strategy. Altera has claimed that, because they focus all their development energy on a single partner, and because that partner is TSMC, they’re able to deliver better products faster. Xilinx has always claimed that their multi-fab, flexible strategy has always allowed them to pick the best partners for each process generation, and to have a more robust supply chain since they always have two options for manufacturing.
Now, by choosing TSMC as one of their suppliers, Xilinx has taken the “our fab partner is better than your fab partner” argument off the table – along with any timing advantage from one supplier’s line yielding sooner than another on a new process node. Also, with Samsung as a second partner, their bets are hedged in case TSMC has unexpected troubles. Their risk, of course, is that getting rolling on two fabs could take longer than Altera will take getting rolling with just one. Score Xilinx with a rhetorical victory here – but now if Xilinx can’t deliver on a similar schedule – it’s not the fab’s fault.
Xilinx claims they are using the “High-Performance, Low-Power” process from TSMC. Although neither vendor has made it completely clear, we believe at this point that both Xilinx and Altera will be using the “High-K Metal Gate” (HKMG) process from TSMC. Probably “High-Performance, Low-Power” is a euphemism for “Low-Power,” because, given the profile of FPGAs, you can get similar or possibly even better performance in practice from a low-power process than from a high-performance one. In many of today’s designs, performance is not limited by the maximum toggle rate or clock frequency. It is instead limited by the power budget and the density – since FPGA designs tend to gain the most performance by parallelizing critical functions.
Xilinx claims that the next generation will see a 50% static power reduction compared with a “high-performance” process, and a 50% total power reduction versus previous-generation devices. The company is implementing both tool and architectural improvements to reduce dynamic power, including finer-grained clock gating.
Both Xilinx and Altera are working to provide the widest range of devices with the lowest mask-costs and NRE on their part. While Altera announced they would be using their “HardCopy” fabric to kinda-harden some of the IP on their devices, Xilinx is going for the grand unification: all of their 28nm devices will be based on the same architecture. Today, Xilinx offers their Virtex line for high performance and their Spartan line for low cost. With their current Virtex-6 and Spartan-6 families (on 40/45nm) the architectures are very similar, but still different – different enough that the same RTL won’t always synthesize to the same netlist. As a result, we don’t have truly “socketable” IP. Cores that will work great on one family might not work so well – or at all – on the other.
Does the unification of the architecture mean that we won’t have separate “Virtex” and “Spartan” families any more? Since this becomes purely a marketing question, the answer is … “We aren’t saying yet.” Maybe we should have a reader poll and tell them what we think? Weigh in on the comments area at the bottom. What Xilinx is saying is that the unified architecture means that we’ll have truly socketable IP. You’ll be able to much more easily move your IP blocks from high-end devices to low-cost devices and vice-versa without a lot of re-work and headaches.
Xilinx says that their previously announced (click here) collaboration with ARM will come into play in their 28nm families. In particular, the next-generation AMBA AXI interconnect specification will provide a robust method for IP interconnect, making FPGA IP much more plug-and-play. This is great news for – well – all of us, actually. Anything that makes IP easier and more reliable to use reduces design time and cost, improves overall quality, and simplifies verification.
One thing Xilinx didn’t choose to disclose was the performance of their multi-gigabit serial transceivers. Altera told us they expect theirs to operate at 28Gbps, and Xilinx has left us guessing so far. We will guess that, in order to support 400 G standards, the number of transceivers multiplied by the speed will need to give a number in the range of 800 G on the biggest, fastest devices.
All of these changes and innovations are in support of what Xilinx calls the Programmable Imperative (yep, they even put it in italics in their press release – just like that). A programmable imperative, of course, is much more flexible than our old fixed-function imperatives. We’re not sure what language one uses to program the imperative, or if a handy API is included… Oh, sorry. Our mistake.
What Xilinx means by the Programmable Imperative is that with the cost and complexity of other solutions going up, programmable logic solutions become increasingly attractive for a wider and wider range of applications. ASICs, ASSPs, and processor-based solutions (depending on your application and market) continue to fall victim to the FPGA take-over. With each process node, the competitive position of FPGAs versus alternative solutions improves, and the market broadens as a result.
We’re pretty happy about that.