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Throwing Down the Gauntlet

Aldec Makes Waves with Mixed-Language Simulation

Aldec is offering a full-blown, mixed-language HDL simulator for $1995.

It might seem strange to have a feature article about a price reduction. After all, we don’t usually see a story come across the AP newswire with a headline like “Heirloom Tomatoes on Sale for $2.99/lb.” The price of commodity items is well understood to be the product of a magic brew that includes supply, demand, manufacturing and shipping costs, package design, and a host of other intangibles – hardly newsworthy.

So, why is this interesting?

There are two reasons.  

First, for us as FPGA designers, Aldec has offered a new and welcome option.  There has always been a gap in our HDL simulation alternatives between the almost-free-and-less-than-capable simulators included with the FPGA Vendors’ design kits and the premium, ASIC-grade, high-capacity, high-performance, mixed-language simulators offered by EDA companies at a much higher price.  Aldec’s new “Active HDL Designer Edition” brings the capabilities many of us need for high-end FPGA design down to a price point less than half of most of the other high-end options.  At $1995/yr for a time-based, node-locked license, or $2495/yr for the floating version, most of us can buy a copy (even with today’s budget controls) without having to mortgage our corporate souls to get a PO signed off by the board of directors.  (And yes, all corporate soul mortgages are those nasty negative amortization situations where each year you owe more than you did when you started.)

The cheap simulators included with FPGA vendors’ kits tend to be heavily limited – in capacity, speed, and functionality.  Usually, these are OEM versions of simulators from electronic design automation (EDA) companies (most commonly Mentor Graphics ModelSim).  The EDA company negotiates a deal with the FPGA vendor to offer a feature-reduced version of their simulator with the design kit, hoping that many customers will upgrade to the full-price product.  One of the key missing features is multi-language capability, which is growing ever-more important with today’s widespread design re-use across groups, divisions, and companies.  You may write exclusively VHDL, but eventually you’re gonna need some chunk of IP that somebody else wrote in Verilog.  That’s one place you hit the feature wall and need to spring for the expensive upgrade.  The other critical points are capacity and performance.  If you’re designing-in lower-capacity FPGAs (Xilinx Spartan, Altera Cyclone, Actel ProASIC, Lattice ECP/XP), you’ll probably have no real issues.  When you go to the big devices, however, you can easily exceed the capacity limits and practically hit performance limits of a low-cost simulator where your time is worth far more than the difference in simulator prices.  

The second reason this announcement is interesting goes deeper – into the EDA industry’s struggle to re-define itself with the changing reality of the design world. Commercial EDA was really born of the ASIC industry.  Doing ASIC design required sophisticated tools, and some clever people figured out how to exploit economy of scale by developing tools that worked across a wide variety of ASIC vendors.  Commercial EDA caught on, and those tools largely supplanted the in-house tools that had been in use at most ASIC companies.  In the “frenemy” relationship that followed, EDA actually prevailed, with the value-add of most ASIC companies being diminished from one side by the EDA companies and from the other side by giant semiconductor fabs, leaving ASIC vendors with insufficient value to sustain a business.

The EDA industry has always had a disconnect in its own value proposition, however.  EDA sells productivity, but its customers are buying insurance.  EDA vendors  boast about the huge productivity gains their products bring to design teams, and they try to justify the cost of their tools in terms of reduced design cycles, better differentiated products, and so forth.  ASIC designers, however, are typically motivated to purchase the tools, not by the productivity argument, but by their desire to be protected from blame for the re-spin.  With the cost of an ASIC re-spin potentially running into millions of dollars, you don’t want to be caught creating the bug that caused the problem.  If your part of the design is to blame, you need to be able to say that you used the most advanced (read most expensive and most widely-adopted) tools available.  If your synthesis, place-and-route, or verification tool cost tens or hundreds of thousands of dollars, you obviously were taking your design responsibilities seriously.

While fear-of-re-spin marketing worked fine with ASIC teams and their enormous budgets, the EDA companies ran into a different challenge with FPGA designers.  If their productivity/time-to-market value propositions had been real, FPGA design projects would have been just as willing to spring for the big-ticket tools as their ASIC counterparts.  They were not.  Productivity and time-to-market have about the same value to an FPGA design that they do in ASIC, but without the fear of career-limiting failure hanging over their collective heads, FPGA designers took a much more conservative view of the value of EDA tools.  Boosted by the FPGA vendors’ propensity to offer their tools for next to nothing – subsidized by silicon profits – this results in a situation where the market value of EDA tools for FPGAs is much lower than for similar-capability tools intended for ASIC design.

This discrepancy between FPGA tool prices and ASIC tool prices has presented a challenge for EDA companies.  For example, it takes about the same amount of effort to build a good synthesis tool for FPGA as it does for ASIC (probably more difficult for FPGA, actually).  However, the market price strongly favors the ASIC tool – particularly with most EDA companies’ direct sales channels and high cost-of-sales.  If an EDA company made a tool for FPGAs, it had to sell them at a low price to a wide audience.  If it made a tool for ASICs, it sold at a high price to a small audience.  As long as the tools could be clearly segregated into FPGA and ASIC versions, EDA had an out.  EDA companies didn’t have to worry about their low-cost version for FPGA design cannibalizing their high-margin offering for ASIC use.  

The dangerous crossroads of this strategy is HDL simulation.  

When we write HDL, it’s basically impossible to tell whether we’re intending it for FPGA or ASIC design.  In fact, with FPGAs being used as prototyping platforms for most ASIC design projects today, the two domains are inextricably merged at the HDL simulation level.  EDA vendors are thus faced with a situation where they cannot easily split the product into two versions.  Historically, they have differentiated the high-end from the low-cost simulators by crippling the low-cost version – artificially reducing performance, capacity, and feature sets.  Today, however, mainstream FPGA designs have grown in size and complexity to the point that FPGA design teams need ASIC-like simulators, but they’re still only budgeted for FPGA-like prices.  Something has to give.

Making the situation even more difficult, ASIC design starts continue their rapid decline, and with them the number of design teams in the market for ASIC tools.  In order to survive, EDA companies have to find a way to make profitable businesses serving the larger design communities – primarily those doing work in FPGA and PCB design.  PCB tools are easily segregated, and the market for those has been stable for a decade or more.  FPGA tools, however, with their close connection to ASIC methodologies, present both an opportunity and a curse.  Move too quickly into the FPGA space and you lose your margin in ASIC.  Move too slowly and you ride the ASIC horse off into the sunset, making more and more complex tools for a smaller and smaller audience.  

In tandem with Altium’s major price reduction a couple of months back, Aldec’s new price point throws down the gauntlet to the big EDA companies.  Now the larger competitors have to either match the price/performance point these smaller competitors are offering FPGA designers or give up a major opportunity in the FPGA market. It’s not as simple as merely dropping their prices, however.  Big EDA companies typically rely on “major account” direct sales strategies with a fairly high cost of sale, depending on big-ticket purchases.  Making money on a low-margin, wide distribution product like an HDL simulator for FPGAs requires a completely different approach.  The results will be interesting to watch.

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