feature article
Subscribe Now

Retro Revolution

The New Vintage FPGAs

Retro is the new new.

Here in the age of ubiquitous high technology, styles and tastes have turned to the past. Vintage clothing, automobiles from yesteryear, pinup models, antique cocktails, and 60s home furnishings are all the rage with today’s hipsters. “Steampunks”, “Rockabillies”, and “Mods” crowd their respective club scenes. In the audio world, it’s vinyl albums, tube amplifiers, reel-to-reel tape, and horn speakers. Culturally-aware engineers who spend their days worrying about leakage current in 32nm transistors go home in the evening and crank the LP version of Louis Armstrong singing St. James Infirmary on their Caliburn turntables.

It’s no wonder that retro-tech is now making its way into FPGAs as well.  The latest in cool programmable logic devices follows on the proven principles that have fed the retro revolutions in fashion and lifestyle – that form often trumps function when people are making purchase decisions.  You won’t find these FPGAs bragging about the latest process node or the largest LUT counts – quite the opposite.  These paragons of prior-generation splendor boldly wear their micron-scale processes on their sleeves. Fabricated in a completely re-tooled 3-micron Bi-polar process, RetroLogik’s new FP-GT500 series FPGAs take us back to a time that never really existed – when electronic designers truly valued the art of design, and when popping the enclosure open on your latest project could gather a crowd faster than free doughnuts in the break room.

The FP-GT500 series is light on LUTs, with the largest device weighing in at a wimpy 5000 logic-cell equivalents.  The device’s largess, however, is in its luxury.  “We watched every other company in the industry constantly battling for supremacy along the same, tired axes – price, performance, and power consumption,” explains Tim Grissom, RetroLogik’s VP of marketing.  “We knew there had to be another market out there for the more discriminating designer – the engineer who isn’t duped into trying to fit his design into the same, plain old square of silicon everybody else in the world is using.”

A “plain old square of silicon” it is not, as the FP-GT500’s severe aspect ratio and standard dual-inline package are throwbacks to a bygone era of electronic aesthetics.  “We all just thought the DIP was a snazzier-looking package than the BGAs and QFPs you see on all the pedestrian programmable logic out there,” Grissom continues.  “The long, slender form-factor with all those pins on the side really sends the message that this device is going somewhere.”  Of course, a high-end “logiphile” (RetroLogik’s term for their target customer) wouldn’t settle for a plain old production package, even in DIP form.  “We start with the highest-grade ceramic package material and apply forty-two coats of hand-rubbed lacquer finish,” explains Art Newsome, head of RetroLogik’s detailing and finishing team.  “We continue with hand-tooled platinum pins, designed to a proprietary pitch.  On the LX-edition, the platinum pins are then electroplated with 24K gold.”  The proprietary pitch may be a bit of a clever marketing gimmick, however, to prevent the FP-GT500 from ever landing in an off-the shelf commodity DIP socket. RetroLogik manufactures their own, ferrofluid-cooled sockets, specifically for the devices.  While some may balk at the price, $4,000 for a socket is a minor line item in the high-flying world of retro FPGAs, where total programmable platform prices with all the accessories can easily run into the high five figures.

When we looked at the company’s prototyping/development board, however, the classic-blue hand-rubbed finish was nowhere to be seen.  A large, finned heat sink covered the top of the device, and the fins were red-hot and glowing.  We asked about the device’s power consumption.  “This baby’s got orders of magnitude more power than your garden-variety FPGA,” Grissom explains.  “That’s one of the reasons we went with the bipolar process.  We custom machine the heat sink from a proprietary alloy and manually inlay the chrome logo work you see there.  In fact – a little inside story here – in our lab, one of the traditions when a junior tech gets promoted to senior technician is to brand their upper arm with the RetroLogik logo using an operating device.  It’s an informal thing that started a couple years back when two techs were engaging in a little horseplay in the lab.  The company doesn’t condone it, but I still occasionally see a new senior tech walking around with a short-sleeved shirt and a bandage, or hear a sizzle and a scream when I walk past the lab door.”

Building an FPGA whose very purpose seems to be to expend large amounts of power accomplishing very little may seem socially irresponsible in this age of concern over greenhouse gases and global warming.  Grissom has a perspective on this as well.  “Yeah, we hear a lot about these other companies and their chilly-little Zero-power Maximum CoolRunning Arctic Igloos.  Our FPGAs are just “cool” in a completely different way.  Also, if you look at power consumption in terms of style-per-kilowatt, none of the other competitors even comes close, so it really just depends on what you’re trying to measure.  Our fun-to-carbon-footprint ratio blows everybody out of the water.”

Nothing is conventional about the FP-GT500, including the clocking scheme.  The family includes a special external PLL that generates the somewhat unorthodox clock signals required by the device. Grissom explains, “You just can’t get the precision we’re looking for with an on-chip PLL.  We decided to go with a discrete clock platform instead.  Our jitter is more than 100 times lower than other FPGAs on internal logic clocking.”  We didn’t understand the need for low jitter on internal clock signals, so we asked for clarification.  “With the kind of clocks those other guys use, your clocking is all over the place,” Grissom bristles.  “Logiphiles just won’t settle for that kind of inaccuracy.  But low jitter is just a minor factor.  What really makes our external PLL cool is the use of sinusoidal clocking.  You see, with a typical square clock – all those transitions are trying to happen exactly on the clock edge – you get SSO (simultaneous switching output) issues.  We generate a pure sine wave as a clock signal.  That way, each transistor can trigger whenever it naturally wants to in the voltage swing, and SSO is dramatically reduced.”

We asked how the sinusoidal clocking scheme affects timing analysis.  “We tell people not to run it [timing analysis],” Grissom explains.  “All that time and effort spent worrying about slack times and the like causes too many designers to lose sight of the more esoteric side of logic operation.  You see, Harley Davidson made a franchise – no, an auditory icon — with just the sound of their motorcycles. We are doing the same thing with logic signals.  We say that our FPGA doesn’t click – it sings!”

The RetroLogik FP-GT500 is also launching with innovations in IP cores.  Not to be outdone by Xilinx’s MicroBlaze, Altera’s Nios, and Actel’s ARM Cortex soft-core processor IP offerings, RetroLogik has their own spin on the proprietary processor core.  “We thought long and hard about what kind of processor architecture really resonated with the logic-design experience we were trying to create with the GT500. The typical RISC architectures just didn’t have the vintage-cool feeling we were after.  We kicked around a lot of options, but the RA-TM just seemed a natural.”  The RA-TM™ stands for “RetroLogik Advanced Turing Machine,” a soft-core processor architecture that implements the Universal Turing Machine (UTM) instruction set with virtual “tape” supplied by off-chip flash memory.  “A lot of people just throw a processor architecture on an FPGA without doing any significant tuning,” Grissom observes. “We squeezed every last ounce of performance out of those Left, Right, Read, and Write instructions, and our No-op is the fastest in the industry.  Our UTM-targeted C++ compiler is still under development, however, and we hope it will be released a few quarters after silicon ships.”

Speaking of shipping, RetroLogik has abandoned the traditional distribution channels for FPGAs as well. Grissom is proud of RetroLogik’s distribution plan.  “Look at your other limited-edition vintage items – none of them are sold through distribution.  We decided to make the FP-GT500 family available exclusively through eBay auction.”

One place the FP-GT500 is not unique, however, is in pre-announcement.  “The family should be ready for our early-adopter customers to evaluate the PowerPoint slides that explain what will be on the datasheet soon,” Grissom concedes.  “Production devices will be ready sometime after that.”

Until then, many of us will be impatiently pressing “refresh” in our eBay windows.

Leave a Reply

featured blogs
Apr 20, 2018
The thing everyone always wants to know about CDNLive EMEA, since it is held in Munich in May, is "Will Bayern München be staying at the hotel?" during the conference, like they did a couple of years ago. The good news is that Munich is still in the European Ch...
Apr 19, 2018
COBO, Silicon Photonics Kevin Burt, Application Engineer at the Samtec Optical Group, walks us through a demonstration using silicon photonics and the COBO (Consortium of Onboard Optics) form factor.  This was displayed at OFC 2018 in San Diego, California. Samtec is a fable...