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Reducing Test Time and Cost for an Advanced Wireless Device

Designing wireless infrastructure chips at 65 nm and below introduced subtle failure mechanisms previously unobserved at larger process nodes. These new failure mechanisms, along with the requirements for better self-test in the field and limitations on available IC pins to interface with automated testing equipment, have resulted in tougher test requirements at STMicroelectronics.

STMicroelectronics’ advanced designs must be of the highest quality for demanding end-product applications. We use in-system test to ensure the device is functioning properly without having to remove it from a board or system. This typically requires a vectorless solution (i.e., one requiring no external tester) such as logic built-in self test (BIST), although vectors can also be applied by an external tester for maximal coverage. Normally, an acceptable level of test coverage for in-system test can be achieved with pseudorandom patterns that target stuck-at and transition faults.

But these devices also require additional test patterns to meet STMicroelectronics’ rigid targets for manufacturing test coverage, which includes being able to identify new failure mechanisms. New types of defects cannot be detected with traditional test methods that target stuck-at faults [1]. Testing these devices requires additional deterministic patterns that include coverage for at-speed and bridging faults. These patterns are capable of identifying the majority of new failure mechanisms and minimizing the number of defective parts shipped to customers. Along with these new requirements, the volume of test data has dramatically increased, but we use scan compression during production test to maximize the coverage while minimizing test time and tester memory allocation.

The pin interface required for logic BIST can be reduced by using a standard IEEE 1149.1 [2] test access port (TAP) controller. Internal scan chains are masked using the TAP interface to ensure that pseudorandom patterns can be applied even if faulty chains are encountered. When short scan chains are used, masking one or a few chains has little effect on test coverage.

This case study illustrates how we applied a combination of logic BIST (LBIST) [3], low-pin-count scan test [4], and boundary scan [5] to satisfy critical product-quality requirements for a wireless infrastructure device with approximately 1.8 million gates.

Test Implementation

The chip interface provided 100 pins that could be used to access 50 tester scan channels. Two clocks were supplied through primary input pins in functional mode, while others were internally generated by two phased-locked loops (PLLs) for in-system test. Insertion of the scan chains, logic BIST, scan compression, and boundary scan hardware was done with commercially available software applications. The test patterns also were generated and simulated using these tools.

Setting up the test logic for this design (Figure 1) started with the latest version of the core netlist. The flops were connected into 2,302 internal scan chains; the longest chain had 59 flops. Design rule checks were performed during scan insertion to ensure there were no major testability issues.

Figure 1: Design-for-test implementation started with the latest version of the core netlist. The final synthesized netlist included scan test, built-in self test, and boundary scan logic.

The design contained 123 memories that needed to be tested with memory BIST and bypassed during logic BIST. In scan mode, deterministic patterns were applied twice to the memories: once with the memories in bypass mode, and later with the memories defined as sequential elements. This enabled the automatic test pattern generation (ATPG) tool to target the memory interface in functional mode and at functional clock speeds when generating vectors for use by an external tester. Ideally, test patterns should be applied using at-speed functional clocks to ensure testing as close to functional speeds as possible [6].

For this design, scan cell captures in functional mode were performed using PLL clocks. All memories were verified using internally generated PLL clocks. BIST and ATPG shifting as well as boundary scan logic used slower clocks to avoid unnecessary timing and routing constraints on shift paths.

Gating logic was added to the end of scan chains to allow them to be masked while in BIST mode. The masking logic was controlled by a data register accessible through the boundary scan TAP pins. This capability made it possible to mask any scan chain in-system so that faulty scan chains did not cause the BIST test to become unusable.

The next step was to insert observe and control points into the netlist to reduce resistance to pseudorandom patterns and increase controllability and observability. Although test points were unnecessary for scan test, they enabled BIST patterns to achieve higher fault coverage more quickly. X-bounding logic was also added to prevent any unknown (X) states from being captured into the scan chains and propagating to the multiple-input shift register (MISR).

After creation of the BIST-ready netlist, the BIST controller logic, embedded deterministic test (EDT), i.e., pattern compression, logic [7], and boundary scan logic were generated in RTL. Once synthesized, additional scan chains were inserted into the logic BIST controller so that deterministic EDT patterns could test the BIST controller during manufacturing test. This increased the scan chain count to 2,508.

After insertion of all test hardware, pseudorandom patterns for logic BIST and deterministic patterns for ATPG were generated and verified by simulating with full timing. ATPG patterns targeted stuck-at, transition, and bridging fault models. This approach provided high-quality manufacturing test patterns that effectively identified defects in silicon.

Internal Clocks and Resets

All internal clocks and resets for this design were generated using two on-board PLLs. In test mode, it is ideal to use the internally generated clocks to ensure testing at functional clock frequencies. For in-system test, a single PLL is activated and all clocks are generated by proper division factors inside the logic BIST clock control logic.

Control signals for the PLLs are generated internally, and these signals configure the related clocks and resets for various functional and test scenarios. The following are some of the ways in which clocks can be used for the various test scenarios:

  • Test logic reset.
  • Stuck-at fault/bridge fault application: All clocks and resets are controlled by primary inputs to multiplex and configure internallygenerated clocks properly.
  • Transition fault application: During shift, PLL internal clocks are bypassed to use slower shift clock. During capture, PLL-generated clocks are used.
  • Logic BIST: Uses a divided PLL clock for shift and the internal PLL clock during capture.
  • Memory BIST: Internal clocks are used. External clocks are available only for debug reasons in production test mode.

For this design, a test clock was defined at the core level for each generated clock domain, allowing automatic insertion of lock-up cells needed to solve potential scan-chain shift problems when crossing the domain boundary by registering the data for an extra half clock cycle on the side of the domain being exited to ensure that the data is correctly captured in the new domain. Parallel capture violations were avoided by using a “dynamic” condition on the test clocks during pattern generation; that is, only test clocks that don’t interact with each other were concurrently pulsed in the capture cycle.

For manufacturing test, all clock interactions were automatically programmed by the ATPG tool to ensure proper coverage of faults within and between clock domains.

Logic Built-In Self-Test

Before implementation of logic BIST hardware, the design was verified for any testability issues using design rule checks. At the same time, scan chains were inserted into the netlist. Given that logic BIST and EDT hardware can drive many internal scan chains, 2,302 scan chains were inserted along with muxing logic to enable selection between logic BIST and EDT hardware.

Control and observe test points were necessary to improve testability of areas of the design that were resistant to random patterns to meet the high in-system coverage requirements for this design. The logic BIST insertion tool was given the flexibility to insert as many test points as needed to reach the desired testability levels. As a result, 10,000 control points and 3,606 observe points were inserted into the design. Additionally, 2,402 muxes were inserted to bound potential X sources (unknown states) that may propagate to the MISR and corrupt the final BIST signature.

The BIST controller logic, shown in Figure 2, was comprised of a pseudorandom pattern generator (PRPG) to drive the scan chains and a MISR to compress the circuit responses into a final signature.

Figure 2: The BIST controller logic consisted of a pseudorandom pattern generator to drive the scan chains and a MISR to compress the circuit responses into a final signature.

Because pseudorandom test pattern generation tends to have a coverage response that falls off over time, a multi-phase test pattern insertion (MTPI) strategy was used to accelerate test coverage. The BIST controller was set up to apply as many as 1,000,000 pseudorandom patterns in multiple phases, each phase initiated by changing the value of one of the inserted control points whenever the rate of coverage increase leveled off, as determined by noting the number of faults that had not yet been detected. As shown in Figure 3, activating a phase by changing control points accelerates the increase in test coverage throughout the pattern application process. This is unlike typical BIST pattern application where test coverage increases slowly and more patterns are required to reach the optimum test coverage. For this design, eight phases were used.

Figure 3: In this example of using multiphase test-point insertion (MTPI), the surge at the beginning of each phase allowed higher test coverage to be achieved more quickly with fewer patterns.

All patterns were fault-simulated to calculate the final test coverage for each fault type. The BIST controller pulses multiple clocks during the capture cycle to detect transition faults within and between various clock domains. There are two ways the clocks can be generated for testing a fault. Using a “launch-off-capture” scheme, two clock cycles are generated after scanning is complete and when the circuit is in “normal” mode: the first “launches” a value change at the start of the paths being tested and the second captures the result if it gets to the end of the path in time. By contrast, “launch-off-scan” gets a jump on things by using the last scan clock to launch the test, meaning only one more clock cycle has to be generated to capture the result. Applying patterns using launch-off-capture provided more accurate transition fault coverage than launch-off-shift because it more accurately mimicked the design’s functional behavior. This step also calculated the final MISR signature that was used to verify proper operation in-system. After running the test in-system, the MISR signature was shifted out using the TAP controller and compared to the signature value calculated after fault simulation.

If faulty chains were encountered in-system, masking logic was used at the end of each scan chain to prevent the faulty chain from being observed by the MISR. A feature of the logic BIST insertion software used the chain masking information to fault-simulate the BIST patterns and calculate the new test coverage. Although test coverage will be lower with masking, this method enables the BIST logic to be usable in the presence of faulty chains. The final MISR signature was recalculated and new test benches and patterns were generated.

All pseudorandom patterns were simulated with full timing in a logic simulator to ensure that timing issues caused no mismatches. To speed up this simulation, the logic BIST insertion tool was used to generate test benches that initialized the PRPG and MISR with proper seed values and ran a small number of patterns. Each test bench was run for 10,000 patterns to validate proper operation using best- and worst-case timing. This automated flow for parallel processing enabled simulation of 1,000,000 patterns in less than two days — significantly less than the original time estimates for simulating all patterns sequentially.

Boundary Scan

A key component of board and in-system test, boundary scan logic provides a standard interface for accessing all on-board test logic. Boundary scan logic was inserted after logic BIST and memory BIST logic to provide the connectivity to the TAP controller.

A common interface of the test interface logic for many STMicroelectronics designs is the test mode controller (TMC). The TMC provides access to memory BIST controllers on the device and includes a shift register for starting BIST tests and capturing the results. By connecting this register between test data input (TDI) and test data output (TDO) ports of the TAP interface, no additional top-level pins are required. An additional advantage is that all memory BIST operations can be performed at the board and system level.

The generated boundary scan logic we used contained the following components:

  • IEEE 1149.1 TAP controller
  • Bypass register
  • Instruction register
  • Boundary scan register containing IEEE 1149.1 standard cells for all device pins
  • Device identification register
  • A user-defined instruction and data register to configure the test mode controller
  • Three user-defined instructions and data registers to run memory BIST and access results after test is complete
  • A user-defined instruction and data register to check locking status of PLL and to control the PLL
  • A user-defined instruction and data register to run logic BIST and access results after test is complete
  • A user-defined instruction and data register to selectively mask any scan chain output.

A boundary scan description language (BSDL) file was generated to provide standard board and system access for the above components. Board test generation tools use the BSDL file to understand the IEEE-compliant hardware and to generate safe and effective test patterns that verify connectivity to other devices on the board.

All boundary scan logic was verified by simulating generated test benches at gate level and by applying boundary-scan-specific test patterns during manufacturing test.

Test Compression with EDT

EDT logic was inserted parallel to logic BIST to drive the internal scan chains with deterministic data and was selectable through a top-level pin. Depending on manufacturing or in-system test requirements, multiplexers on the input of each scan chain can be configured in EDT or LBIST mode by the top-level select pin. EDT patterns were applied to the core as well as the BIST controller during manufacturing test to detect defects in the logic BIST controller.

Pattern generation was completed using a process similar to ATPG for a design with uncompressed scan chains. Scripts generated during the hardware insertion phase were used to generate at-speed, bridging, and stuck-at test patterns. Before pattern generation for a specific fault type, each pattern set was fault-simulated for other fault types to ensure that new patterns were generated to only detect faults that had not already been detected by other pattern sets. Scan data volume was reported during pattern generation of compressed and uncompressed scan chains to measure the amount of compression provided by EDT.

Embedded deterministic test provides high compression of scan test data and test application time [8]. As shown in Figure 4, EDT inserts a decompressor on the input of the design’s scan chains that enables automated test equipment to load the scan chains using compressed stimuli. The circuit response is compacted into few scan channels and compared to compacted responses stored on the tester. The advantage of this approach was the ability to load large number of short scan chains with tester stimulus that can be compressed dramatically. By loading short scan chains cycle by cycle, test time was also dramatically reduced. Less test application time and less data stored on the tester reduced the cost of testing each device while still maintaining high test quality.

Figure 4: Embedded deterministic test hardware includes a decompressor on the input of the design’s scan chains that enables automatic test equipment to load the scan chains using compressed stimuli.

One important requirement for manufacturing test is the ability to diagnose tester failures quickly and accurately. EDT technology enables failure diagnosis using the same compressed patterns that are applied on the tester, thus eliminating the need for any bypass patterns [9]. This also makes diagnosis possible as an online process on the manufacturing floor so that useful information can be collected for yield analysis.

Test Results

For this design, logic BIST coverage was 98% for stuck-at faults and 83% for transition faults. A total of 1,000,000 pseudorandom patterns were applied in 2.5 seconds to reach this coverage. The stuck-at and transition fault (SAF and TF) coverage profile for the BIST patterns are shown in Figure 5. At the start of each multi-phase test point insertion phase, the jump in test coverage indicated a change in active control points.

Figure 5: Stuck-at (SAF) and transition fault (TF) coverage profiles for the logic BIST patterns.

For manufacturing test, the deterministic stuck-at test coverage for this design exceeded 99% for scan and boundary scan patterns that verified normal operation and various TAP test modes. This includes coverage of the logic BIST controller which was scanned and tested by EDT. At-speed (transition) test coverage was approximately 87%.

Final deterministic scan pattern count was approximately 4,500 for stuck-at and transition faults. This resulted in approximately 24 Mb of scan data.

Through the use of EDT hardware, the final deterministic data volume was reduced by a factor of 28 when compared to 678 Mb of uncompressed scan data volume. Compared to uncompressed patterns, no test coverage was lost because of the application of compressed patterns.

Note that the typical area added to a chip due to EDT is about 0.2-0.5% of the design, while the area cost of LBIST is typically in the range of 2-3% of the design.


Advanced test methodologies enabled us to combine high-quality manufacturing test and in-system test for our 65-nm wireless infrastructure device. The combination of in-system and compressed scan hardware on the same device introduced some challenges in the implementation flow and timing closure. Nonetheless, the benefits of using high scan test compression with in-system test provided significant value, meeting the target requirements for high-quality coverage while reducing the time and cost of testing each manufactured device.


1. G. Aldrich and B. Cory, “Improving Test Quality and Reducing Escapes”, Proceedings of the Fabless Forum, Fabless Semiconductor Association, 2003, pp. 34–35.

2. IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture –Description.

3. “Logic BIST Application and Usage,” Mentor.com

4. “Combining Compression with Fewer Pins Dramatically Saves I/O during Multi-Site Test,” Mentor.com

5. BSDArchitect, Mentor.com

6. Lin, X., et al., “High-Frequency, At-Speed Scan Testing,” Design and Test of Computers, Sept-Oct 2003.

7. Embedded Deterministic Test – DFT Technology for High-Quality Low-Cost IC Manufacturing Test.

8. J. Rajski, et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proceedings of the International Test Conference (ITC 02), IEEE Press, 2002, pp. 301–310.

9. A. Leininger, et al., “Compression Mode Diagnosis Enables High Volume Monitoring Diagnosis Flow”, International Test Conference 2005.

About the Authors 

Alessio Pricco is a Project Leader for ASIC designs in Communication Infrastructure Division in STMicroelectronics, responsible of technical aspects of devices under development. He previously worked as a DFT expert/front-end designer in Italtel, Toshiba Electronics, and Accent. Pricco has an MS in Computer Engineering from Torino Polytechnic.

Jay Jahangiri is a Technical Marketing Engineer for Mentor Graphics’ Silicon Test products, responsible for development of product requirements and providing technical consultation to customers. He previously worked as a DFT engineer for Texas Instruments and Raytheon. Jahangiri has a BS in Electrical Engineering from the University of Texas at Arlington and an MBA from the University of Phoenix.

Kan Thapar is a European Product Specialist for Mentor Graphics’ Silicon Test products. He works with Mentor’s European customers to implement advanced test implementations in their ASIC designs. He previously worked as a VLSI/ASIC designer at GEC Hirst Research Centre on advanced telecommunications, multimedia, space, and military designs. Thapar has a BS in Mathematics and an MS in Digital Systems from Brunel University, UK.

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