feature article
Subscribe Now

Lattice Strikes Back

Low-cost, Low-power with SerDes - New ECP3

When Xilinx and Altera made their recent announcements of new low-cost, SerDes-havin’ FPGA families, we pointed out that Lattice Semiconductor had started this pie-fight a couple of years back when they introduced ECP2M – the first low-cost FPGA platform with multi-gigabit serial transceivers. Now that they have taunted the two bigger players into the melee, Lattice is raising the stakes with a brand-new family that boasts more performance, higher density, less power, and more on-chip memory than its sand-kicking predecessor.  

 

The new ECP3, fabricated on Fujitsu’s advanced, low-power 65nm process, is touted as the industry’s lowest power SerDes-capable FPGA family.  Lattice has thrown a considerable amount of power-related design optimization at ECP3, including variable channel widths, optimized transistors, and re-tuned placement and routing algorithms that yield better power results.  While power is perhaps the most difficult metric to cross-compare (your mileage will vary – a lot – depending on your design and stimulus…) their datasheet numbers make a good case with very low static power (under 250mW typical on a 150K LUT device).  

 

In addition to enjoying low power consumption, many of us like to know how much power we’ll be using.  Lattice offers a highly-accurate power calculator with their ispLEVER tool suite – claiming that calculated power is within 10% of actual silicon.  

 

The new family is aimed at cost-sensitive high-performance applications such as remote radio heads – where power is also always at a premium.  These applications place high demands on high-speed serial I/O, and so SerDes features are the big part of the story with ECP3.  The family offers up to 16 SerDes transceivers operating at up to 3.2Gbps each.  If you think that sounds like the same numbers they sold with their previous ECP2M family, you’d be right.  However, the devil is in the not-so-hidden details.  The new “enhanced” SerDes in ECP3 supports a wider range of serial standards – including XAUI, GbE, SGMII, PCIe v1.1, Serial RapidIO, OBSAI, CPRI, and SMPTE.  Jitter compliance is up to the higher XAUI and SMPTE standards, and power consumption has been reduced to 90mW per channel at the full 3.2 Gbps speed.  If all this capability has your eyes sagging toward closed, the transceivers include built-in transmit pre-emphasis and receive equalization as well.  

 

In addition to the high speeds, single-pin SDI multi-rate support on each channel allows individual rate selection even though transceivers are arranged in quads.  Native low-speed support goes down to 250Mbps without over-sampling – a feature sometimes overlooked in high-performance transceivers. One of the places the previous family took criticism was a lack of capability to support the SerDes, and ECP3 has convincingly overcome this deficit.  On-chip RAM has been increased to as much as 7Mbits, with single-port, dual-port, and pseudo-dual-port arrangements available in a rich selection of widths and depths.  Memory performance up to 390MHz allows the kind of caching and buffering often required in demanding SerDes applications.  

 

Also impressive is the external memory support – including DDR3 at up to 800Mbps (400MHz).  Beyond the headline DDR3 (with support for industry-standard DIMMs) is also DDR2, DDR, RLDRAM I/II, and QDR I/II.  Designing in DDR3 today could let you take advantage of favorable commodity memory prices when it comes time to go into volume production, and built-in support will further reduce the final system BOM for cost-sensitive applications.  The devices sport six general-purpose I/O banks per device, with a broad range of standards supported, including LVDS up to 1Gbps.  

 

In applications like Lattice is targeting, integration to reduce cost is a big factor.  With almost every communications design having a demanding DSP component, Lattice has increased the DSP resources on the new family.  ECP3 devices contain as many as 160 sysDSP blocks – each delivering up to two 18×18 multipliers (or a variety of other DSP configurations like 36X36, 18X36MAC, and 18X18MMAC). The DSP blocks can operate at up to 500MHz – allowing significant acceleration for integrated DSP functions such as CFR.  By keeping the DSP acceleration on-chip, overall power consumption is reduced as well.

 

The new devices support all of Lattice’s previously-announced (and very robust) configuration options including (in addition to standard jtag) parallel burst mode flash for fast configuration, automatic multi-boot allowing multiple images to be stored and swapped, pre-engineered remote field update with “TransFR,” and bit-stream encryption for secure configuration.  In many of the emerging markets, where FPGAs offer flexibility advantages, these configuration options bring that flexibility to life by making re-configuration a more viable solution.  

 

By the numbers, the ECP3 family ranges from 17K-149K LUTs, from 552 to 6,850 Kbits block RAM, from 24 to 320 18×18 multipliers, and from 4 to 16 3.2Gbps SerDes channels, in addition to 222 to 586 user I/O pins.  The 70K and 95K devices are in production now, with the remainder of the family scheduled for later in 2009. Lattice tends to do new device announcements only after their products have undergone early-access use and are actively in production, so the delay from announcement to availability is much less than with most FPGA companies.

 

Lattice is also rolling out three development boards with the new family, a Serial Protocols board, an I/O Protocols board, and a video board – anticipating a mainstream application of ECP3.  The family is also supported by the company’s ispLEVER tool suite, as well as third-party tools.  

 

Although the company has struggled from a business perspective for the past couple of years, Lattice continues to bring top-flight, well-differentiated products to market.  While they may not have the marketing muscle and resources of their two larger competitors, their engineering teams are not willing to give up without a fight, and their devices continue to find enthusiastic adopters who appreciate their distinguishing features. In the case of the new ECP3, we expect that the combination of low power, low cost, and high capability in a SerDes-enabled FPGA will bring a lot of those design teams enthusiastically to the table.

Leave a Reply

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...