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Who’s Winning?

Early Returns in the FPGA Races

Let’s face it, we’re a competitive species.  People like to compete in just about everything they do.  We’re not psychologists, so we can’t speculate with much authority on the Ids and Egos that drive our drives to win, but we can certainly see the results – in everything from our obsession with sports to our capitalist system of business.

An important by-product of our competitive nature is our attention to score keeping.  We constantly strive to establish metrics by which we measure our progress and success – against others, against ourselves, or against arbitrary goals and standards that we aspire to reach.  For the masses, simple metrics work best – who had the highest score at the end of the game?  For the more sophisticated among us, however, (say, perhaps, for people like engineers) the slicing and dicing of metrics becomes an end unto itself.  Did our favorite pitcher do a good job despite his team’s losing efforts?  How does our latest design stack up in compute performance per Watt? 

In the FPGA market, there are a number of companies striving for supremacy.  Of course, the easy measures of success are well-publicized figures like “market share.”  However, in a community as intelligent and competitive as ours, we want to dive much deeper – to establish a scorecard that will give us ultimate visibility into the status, the trends, and the opportunities that exist in a complex, multi-dimensional competition such as this.

Let’s take a quick look at the teams, the rosters, the product portfolios, and the strategies and make some qualitative calls to answer the question that’s burning in everyone’s minds – “Who’s Winning?”

First up, the league of FPGA vendors.  This is, of course, the “A” division.  While other companies dabble in FPGAs – allocating more or less budget to their projects in the space depending on expected returns, FPGA vendors are “all-in” all the time.  To paraphrase the fable of the ham-and-eggs breakfast – the FPGA vendors (like the pig) are “committed,” while the other players (like the chicken) are “involved.”

In the FPGA vendor category, the “easy route” would be to call the race based on simple market share numbers.  Here, for the past decade or so, Xilinx is #1, Altera #2, Lattice Semiconductor #3, Actel #4, QuickLogic #5, and everybody else (retirees like Cypress, new entrants like Achronix and SiliconBlue, etc.) occupies one of the “trace element” slots from 6 to infinity.  Furthermore, the top two own a vastly disproportionate share of that market, with Xilinx and Altera combining to hold an estimated 60-90 percent of the overall market, depending on which year and whose statistics you use.  We have only one word to describe this scoreboard:  “Boring.”  And “Inaccurate” – oh, wait — that’s two.

The FPGA companies themselves seem to think that “who’s up on the latest process node” is a valid way to call the game.  Given that metric – Altera is now #1 with announced products at 40nm, followed by Xilinx, Achronix, and SiliconBlue at 65nm, Lattice at 90nm, and Actel and QuickLogic at 130nm.  Fair?  No way.  Interesting?  Somewhat.  Real information?  Actel and QuickLogic should be in different categories, as they use unconventional technology that isn’t based on standard CMOS process – Flash (not the commodity NAND type) and anti-fuse.  It will always be harder to get those working on a new process node than SRAM-based fabric of more mainstream FPGA technologies.  Lattice has placed their stake on a fab partnership with Fujitsu, and the combination has worked well but has yet to announce 65nm production. 

Achronix and SiliconBlue both launched from scratch at TSMC’s “current at the time” 65nm node, Altera surfed TSMC’s latest and greatest and went to 40nm earlier than anyone in the field, and Xilinx’s focus stayed on expanding their 65nm Virtex-5 portfolio, their 90nm Spartan-3 line, and moving more slowly with their multi-fab strategy to 45 and beyond.  Industry rumors abound that Xilinx will skip 65nm altogether with their low-cost line and will make their next big announcement at something around 45nm.  Depending on who you ask, Altera was more motivated to get to 40nm because of starting out behind on 65nm, or Xilinx fell behind in their 45nm development schedules due to weaker foundry choices.  Which is true?  Hard to guess.

What if we look at more measurable metrics like speed, power, and density?  That should be pretty clear-cut, right?  Wrong-o, grasshopper.  Here, datasheets are next to useless, marketing claims are highly exaggerated, and real-world apples-to-apples examples are almost impossible to come by.  Have any of your own? Post them on Journal Forums! 

On the speed front, Achronix has come out blazing with claims of 1.5GHz clock frequencies and massive I/O and DSP capability.  Admittedly, their “pico pipeline” makes this not a straight-ahead apples-to-apples comparison with mainstream FPGA technology, but we’d venture a guess that there is a category of applications for which Achronix FPGAs will reign supreme in performance.  The high-end Altera and Xilinx chips will bring up the next two slots – anecdotal reports from our readers show a number of situations where Altera’s Stratix III edges out Xilinx’s Virtex-5 in real-world design performance.  A similar number of reports, however, give the edge to Xilinx in performance per cost where a more-tailored version of the FPGA gives an optimal mix of performance-critical resources such as DSP blocks, RAM, multi-gigabit I/O, and embedded processors.  Altera’s recently announced 40nm Stratix IV should at least temporarily reign supreme once in high-volume production, however.  Xilinx’s response with a similar-performing process node is now market-critical for them.

When it comes to power consumption, two smaller players dominate.  Actel has almost completely re-branded their company around a low-power mantra, and their flash-based FPGAs can deliver the goods.  Similarly, startup SiliconBlue has jumped into the low-power fray with more conventional FPGAs (SRAM at 65nm) that have considerable power advantages.  While market leaders Xilinx and Altera continually spar over each others’ power consumption claims, neither is the leader in low-power FPGA technology.  To be fair, however, none of the companies that produce a “low-power” FPGA has a product that competes with the high-end lines like Xilinx Virtex and Altera Stratix.

In the density competition, the measurement gets REALLY dicey.  It is easy to award the “highest density FPGA announced” award right here and right now to Altera for their 40nm Stratix IV.  However, once other companies are up on the same process node, the density battle will most likely fall back into the debate-friendly chasm of confusion.  In the old days, we could count 4-input LUTs and announce a winner.  Marketing genii in the two top companies, however, FUDed even that simple scorecard with claims of carry-chain supremacy that yielded other than a 1:1 LUT-4 comparison.  Other vendors like Actel that use something analogous to a 3-input LUT simply stuck with the old, inflated, “system gate” measurement.  Today, nobody measures fabric with anything that’s very close to comparable.  Xilinx and Altera have each settled on their own formula for converting today’s wider logic cells/elements into an equivalent number of old 4-input LUTs.  The rest of the industry adopts various versions of either that scheme or Actel’s “system gates.”

Measuring the fabric is pretty passé these days, however.  Now, fabric is but one of many resources that add value and transistors to a typical FPGA.  Other hard-wired IP blocks such as DSP (multipliers, MACs, ALUs), memory, hard-core processors, clock generators, complex I/O blocks, and multi-gigabit transceivers can each be scored independently.  Xilinx has adopted a strategy of providing a vast array of parts with varying mixtures of these elements – all in an effort to optimize silicon area, cost, and power for particular classes of applications.  Other vendors stick primarily to scaled, proportional helpings of each element, depending on the market they’re most trying to attract.

Right along with the density battle is the quest for the smallest footprint.  As of today, Actel is the “tread lightly on the board” champion with packages as small as 3x3mm and single-chip operation that eliminates the need for external configuration circuitry.  Other non-volatile devices such as Lattice’s XP families, Xilinx’s stacked-die Spartan products, and QuickLogic’s and Actel’s antifuse devices also offer the “no extra configuration” footprint advantages.  Beyond that, the practical footprint contest amounts to checking the datasheet to see who offers the number of pins you need in the smallest package your board design team can handle.  Sometimes, the smallest pitch puts demands on board design that are not good tradeoffs for the overall system cost, so beware of jumping on the absolute smallest dimensions.  Here, however, is probably the contest that’s the easiest to call with datasheets alone.

Speed, Power, and Density are only the first three box scores to pop up on our teleprompters.  For those of us deep in the weeds, we need to look at tools, IP portfolios, special-purpose qualifications (for industries like aerospace, automotive and the like), distribution and supply capabilities, AE support, and a host of other sub-category scores to evaluate the true winners in the FPGA vendor category.  On the “reaping the rewards” side, we are equally confounded by the “win today and see the benefits next year” nature of the business as design- and socket-wins that companies capture today don’t translate into big-revenue orders for a long period of time.  We’ll look at these and other measures in future installments of this series.

Next week, we’ll be taking a look at who’s winning some of the “chicken” parts of the industry – design tools for FPGA design.  In many sports, the “B” leagues have more exciting and intriguing play than the majors.  FPGA design is no exception.  Stay tuned for the next article in this series.

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