feature article
Subscribe Now

Exotic Non-Volatiles

A Look at FRAM and MRAM Technologies

[Editor’s warning: this article contains multiple instances of polysyllabic scientific jargon. Reader discretion is advised.]

Two non-volatile memory technologies have been making some low-level play over the last little while, and it’s pretty easy to confuse the two or think that they’re somehow related. One is a relative old-timer; one is a newcomer. But for many designers, they may both be unfamiliar. In fact they have pretty much nothing to do with each other from the standpoint of how they work. The question that remains, however, is whether they will vie for the same designs.

The first is the more venerable of the two, FRAM, or FeRAM: Ferroelectric RAM. Now the “ferro” bit in there would indicate iron, and we all know that iron is magnetic. And in fact, the name “ferroelectric” is derived by analogy to “ferromagnetic.” Its operation is even said to be similar to that of the ferrite core memories of yore. So it’s easy to slip into the assumption that FRAMs are somehow related to other magnetic-based memories.

Alas, the storage is not magnetic. In fact, the dang thing doesn’t even have any iron in it. The memory storage mechanism is based on the concept of “ferroelectricity.” Some materials, unlike your normal dielectrics, have rather less straightforward behavior in the presence of an electric field. Called “paraelectric,” they have a non-linear relationship between polarization and field: at higher fields it looks linear, as if it were going to hit the “y-axis” above zero, until you get to the region of lower fields, at which point it curves down to the origin; this is symmetric with respect to the direction of the field.

Take this and add hysteresis, and you have ferroelectricity. The analogy with ferromagnetism seems to me to go like this. Picture a magnet (made of iron, I guess) in a magnetic field that opposes the polarity of the magnet. Strengthen the field, and the magnet stubbornly continues its opposition up until a point when it gives up, capitulates, and you actually re-magnetize the magnet in the other direction. Now instead of opposing the applied field, it’s switched sides, and is fighting for the enemy. If you now reverse the applied magnetic field, the newly treasonous magnet will now be in opposition to the newly reversed field and will maintain that opposition until the field becomes so strong that it once again makes an offer the magnet can’t refuse, so the magnet flips again. Because the applied field has to overcome the magnet’s field before it flips, you end up with hysteresis – you have to “overcompensate” in each direction to get the magnet to flip.

The same basic thing happens, more or less, if you squint, with the electric dipoles in the ferroelectric material. At a certain electric field, the electric dipoles align, and that alignment remains until a reverse electric field is applied that’s strong enough to overcome and reverse that polarization. This means that the direction of the polarization can be used to store information much as a magnet can. But it’s not a magnet. It just works by analogy to a magnet. With ferro; without iron.

The material used is most typically something called PZT: lead zirconate titanate, which is made up of lead titanate, which is itself a ferroelectric, and lead zirconate, which is an anti-ferroelectric – meaning that “rows” of dipoles are alternately polarized in opposite directions, which ultimately cancels out the net polarization. While it’s not necessarily relevant to an FRAM discussion, these materials have numerous other uses. It turns out that ferroelectrics must also be piezoelectric (responding to pressure) and pyroelectric (responding to heat – think temperature sensors).

Ramtron has been the historic FRAM king; the first product was a 4k-bit unit shipped in 1993; they recently announced their 1M memory in a serial version to compete with 1M serial FLASH chips. So where do they compete well? At current production levels FRAMs are more expensive than FLASH, so they need to have some other redeeming characteristic. Which, as it turns out, is their ability to do many fast single-cell writes. Their strength is in write-intensive applications requiring non-volatility. Ramtron started with Sonic the Hedgehog on a Sega machine; nowadays the applications are largely industrial in nature; things like metering (think electric, water, taxi) and datalogging (think oil and gas).

The need to do lots of writing goes directly to the heart of the weakness of FLASH technologies: endurance. You get only at most 100,000 chances to write a FLASH device before you risk running into data retention issues. In addition, FLASH writing tends to be slow, and you can’t write just a single byte or word – you have to erase a block first.

The FRAM technology can be written at bus speed, so there’s no waiting for each write to occur. In addition, the endurance is many orders of magnitude higher than that of FLASH: Ramtron touts 1014 cycles. The power is also lower when writing: because no high voltages are needed, no charge pumps are required to write to the memory.

Because FRAM cells can be written in the same granularity that they’re read (that is, without the need for a block erase), it’s also fair to compare to DRAMs. Clearly, larger memories are available with DRAM, and the cost is lower. But FRAMs use less power because they don’t require any refresh.

FRAMs have typically been sold as dedicated separate chips. Could they be integrated into an SoC? Theoretically, yes. It doesn’t take that much in the way of extra steps, but the kicker is the fact that the PZT is an unusual material and not part of your garden-variety fab. Not only that, but the lead is problematic, so the deposition must be isolated from other steps (and after all that work to become Pb-free!). Plus, the equipment is different. So to date there hasn’t been much in the way of an attempt to include FRAM cells in SoCs.

The other technology up for discussion is MRAM – magnetoresistive RAM. And this time the name is descriptive: magnetic fields are used. And you’ll also hear the science-fictiony-sounding terms “spin torque” and “spin transfer,” referring to some of the quantum-level mechanisms underlying what’s going on. And you will also see references to spin torque transfer (STT) or spintronics as the mechanism behind a specific kind of MRAM, so the terminology varies; STT is the current focus of research, so that distinction is more recent. Am I the only one getting confused?

This technology is much newer; Freescale was first out with smaller versions in 2006 (and is spinning the activity out into a new entity called EverSpin); IBM and Toshiba are also talking about releasing 1GB version soon. Samsung and Hynix announced joint work, and there are also smaller companies dedicated to MRAM work, such as NVE, Micromem, and Crocus. At the recent CICC conference, NEC presented results from their work on an MRAM flip-flop. Their motivation was actually different from that of your typical memory investigation: they were trying to find a way to make a non-volatile flip-flop so that when parts of a circuit are powered down, you don’t lose the state. This is explicitly targeted for SoC integration and for operation at lower voltages.

MRAM cells consist of a dielectric with a magnetic plate on either side. One of those plates is permanently magnetized (or “pinned”); the other isn’t, and it can be magnetized by the circuit. The way the second plate is magnetized is by routing a metal line in a somewhat circular (OK, squarish) path; by running the current in one direction or the other, a magnetic field of one direction or the other is set up to magnetize the plate. I’m sure the quantum-mechanical description is much more impressive, but I’m simple that way.

The cell is read by measuring the resistance of the tunneling current across the dielectric, which changes depending on whether the plates are the same or opposite polarities; this is the so-called “tunneling magnetoresistive effect.” This process is a bit easier to integrate into a standard CMOS flow, since the only additional step is the less exotic dielectric between the plates.

The design of the flip-flop was differential, as most flip-flops are, but that included two MRAM cells, presumably adding some space to the cell (apparently FRAM cells were at one point differential as well). In theory it would seem that a single cell could be used to store the value – unless the issue is error detection, to catch situations like someone accidentally leaving it inside the Large Hadron Collider and polarizing both cells the same way. But the big space-chewer was the write circuitry: it made the cell twice the size of a normal flip-flop. The flip-flop worked as designed, but further effort is being put into reducing the area and the write power.

So… FRAM, no magnet; MRAM, magnet. (By extension, FRAM not affected by magnetic fields; MRAM could be, although Freescale says that disturb fields are an order of magnitude greater than what you would generally find in everyday use.) FRAM has been in production for a while; MRAM is emerging. FRAM has a very very high write endurance rating; MRAM actually has no limit, so infinite (in theory) endurance. FRAM doesn’t appear destined for SoC integration; MRAM does.

Both FRAM and MRAM technologies appear to have some scaling challenges to overcome, although Ramtron claims that FRAM scales better than MRAM. It appears that the ferroelectric effect goes away below certain sizes, which places a physical limit on FRAM. Meanwhile, you can pack magnets only so close together before they start interfering with each other, limiting MRAM. Such simplistic barriers are the kinds of things that have foretold the death of CMOS for years now; as long as there’s a compelling need for the technology, you can expect that someone will be trying to find ways to push out those barriers and extend the technology much further than initially expected.

As to the original question, whether these technologies will vie for the same designs: while it seems like they could in theory, from an SoC standpoint – which is our focus here – they certainly seem to be heading in different directions for the time being. They will probably be duking it out pretty seriously in the off-chip memory arena, but the attention in this journal will be more on MRAM as the technology evolves.

Links:
Ramtron
MRAM developments   

Leave a Reply

featured blogs
Aug 18, 2018
Once upon a time, the Santa Clara Valley was called the Valley of Heart'€™s Delight; the main industry was growing prunes; and there were orchards filled with apricot and cherry trees all over the place. Then in 1955, a future Nobel Prize winner named William Shockley moved...
Aug 17, 2018
Samtec’s growing portfolio of high-performance Silicon-to-Silicon'„¢ Applications Solutions answer the design challenges of routing 56 Gbps signals through a system. However, finding the ideal solution in a single-click probably is an obstacle. Samtec last updated the...
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...