Accellera’s chair, Shrenik Mehta, of Sun, has no truck with the traditional standards process. His view is that it is important to get a standard accepted and in use as soon as possible, particularly in the EDA field. Accellera’s name reflects this, and its method of working is designed to achieve it.
Accellera membership is a mix, reflecting its mission statement which is:
Drive the worldwide development and use of standards required by systems, semiconductor and design tool companies that enhance a language-based design automation process.
And among the systems, semiconductor, and design tool companies that are members of Accellera are Nokia and Cisco, Freescale and Xilinx, and the big four tool companies of Cadence, Magma, Mentor and Synopsys, along with 23 other companies. Accellera also has a designers’ forum with over 4,000 members, who are encouraged to comment and contribute. Member companies are allowed only a single vote each, which is a significant factor in speeding up the approval process within Accellera. Another way in which Accellera speeds up the process is by building on tools developed commercially and then donated to Accellera; this has the added benefit that the standards are not theoretical but based on working products.
Accellera recognizes that the imprimatur of acceptance is IEEE recognition, and once the organization has completed work on a standard, it assigns copyright to IEEE. But while in other areas, IEEE can take a long time to produce a completed standard (work on 802.11n started in 2003, and the standard still seems to be as far away as ever), Accellera standards normally fly through the process, with copyright assignment to final publication taking less than a year in many cases. This is because in drawing up its standards, Accellera always keeps the requirement of the IEEE in mind. It uses, for example, the IEEE template for layout and design, and of course most, if not all, of the interested parties have already signed off on the standard.
As the mission statement says, Accellera concentrates on language-based tools, and since it was formed in 2000 by merging OVI (Open Verilog International) and VHDL International, it has seen 11 standards complete the IEEE approval process, covering VHDL, Verilog, and SystemVerilog, as well as models, libraries, compression, power, and more. (check www.accellera.org). Today there are working parties looking at interfaces (ITC), analog and mixed signal (AMS), the open verification library (OVI) – a library of assertion checkers for design validation – and the exchange of coverage data (Unified Coverage Interoperability Standard – UCIS). The IEEE working group (WG) responsible for version 4 of VHDL (WG P1076) is working within Accellera, and Accellera supports other IEEE WGs.
The starting point is the high-level languages, initially Verilog and VHDL. These were the results of efforts to take circuit design to a higher level of abstraction and are still the backbone of most IC design effort. To take the abstraction even higher, there has been work on “System” languages, such as System C and SystemVerilog. System C is outside the scope of this overview, at least for the present, but SystemVerilog is very much at the centre of Accellera’s activities. On the SystemVerilog.org website, the language is defined as the “…first unified hardware description and verification language (HDVL) standard. … [it] is a major extension of the established IEEE 1364 Verilog language. It was developed originally by Accellera to dramatically improve productivity in the design of large gate-count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow.”
SystemVerilog supporters claim that, as well as being a super-set of Verilog, SystemVerilog incorporates many VHDL-like features, and can, in some lights, look like a superset variant of VHDL. Whether you accept that or not, there is certainly provision to combine SystemVerilog with large chunks of VHDL in developing and verifying a design.
Looking at the work currently in progress and the related road maps, the Open Verification Library (OVL) project is working on a library of assertion checkers. These cover about 50 assertions, such as always, never, one_cold, one_hot and others. The intention is that these provide a vendor-independent interface for validating a design and are provided in open source for SystemVerilog, Verilog-PSL, Verilog, and VHDL. OVL is currently at version 2.1, with 2.2, including more VHDL support, due in the next few weeks. The target is for version 3.0 to be available in Q2 of 2009, possibly with a SystemC implementation and with extensions to SystemVerilog Assertions (SVA).
Another Accellera group looking at assisting verification is UCIS (Unified Coverage Interoperability Standard) whose charter is to ‘Create a standard to support the exchange of coverage data within and between verification related processes.’ They plan to do this by providing a standard definition of coverage terms and metrics and a mechanism for sharing coverage data, such as one or more sets of APIs. The standard will also attempt to provide an extensible framework to allow user-specific coverage data to be exchanged. Unlike the standard Accellera process of starting from donations, UCIS is starting with a clean sheet of paper. An API design document and a High Level Design are both in review.
Making it easier to hook simulation and emulation tools into the main SoC design flow is the role of the Interface Technical Committee (ITC). It published version 2.0 of an interface between modeling tools and the simulator/emulator last year (the Standard Co-Emulation API: Modeling Interface (SCE-MI)) and is working towards a release of version 2.1 in Q3 this year. This will incorporate some fixes and the results of feedback from vendors who are implementing the standard.
Power is a significant issue in all designs, and Unified Power Format (UPF) is working towards a standard format for specifying low-power design intent. Version 1, which looks at the RTL-to-gate design flow, was passed to IEEE in May 2007 after a very fast five-month definition by Accellera. An IEEE standard should be published in 2008, after a process of adding some more design methods and providing better legacy IP support. The Accellera group will then move on to looking at extending from the RTL level up to the system and architectural level and providing better power estimation.
With the increase in mobile communication products, the pressure is on to incorporate analog elements in SoCs that were previously only digital. AMS (Analog and Mixed Signal) work is on creating a unified modeling language. Version 2.3 of the Language Reference Manual is undergoing final edit and review and should be available very soon, and work is beginning on Version 3, which will provide initial integration with SystemVerilog and is tentatively scheduled for a year after the publication of 2.3.
All this work is designed to meet the requirements to provide standards … that enhance a language-based design automation process. But it is not design- or system-language specific. Rather the approach is to be as open as possible and to take the best features from a range of tools. The language wars between VHDL and Verilog may still be rumbling on, and SystemC and SystemVerilog may appear to be at loggerheads. But Accellera appears to be trying to act as peacemakers with the aim of getting all the elements that are needed in the design flow to live in peaceful co-existence and maybe even work together. In an arena dominated by commercial interests, this has to be applauded.
