feature article
Subscribe Now

Power Plays: Raising the Stakes

Synopsys Announces Eclypse for Low Power

The cards having been dealt, he took a peek at his down cards. A king… not bad… a 2… now why couldn’t we be playing “low-card-in-the-hole?” At least he wasn’t playing Texas Hold-em, the only game people seemed interested in anymore, and for reasons that were completely beyond him. There were so many other interesting varieties; hell, these days, even a plain old game of seven-card stud seemed downright novel. Jack showing; time to bet… let’s see that next card.

While not suggesting a random or luck component in EDA products, with broad areas like low power design, building an offering can be much like building a good poker hand: you lay on the features as you can until you’ve got what you hope will be the best hand. And an occasional show of bravado doesn’t hurt either.

So interleaved with our series on low-power design techniques is an announcement by Synopsys of their new Eclypse offering with a focus on low-power design. We’ve covered some of the issues before, and some we have yet to discuss, so we’ll do a bit of review for the former and a bit of preview for the latter.

As testament to the currency of low-power design, even though Synopsys has been adding low-power features over the last few years, they are actually branding their low-power solution as of this release under the Eclypse moniker. Part of this may be a “the time is right” thing, but part of it could reasonably be their completed support for a simple unifying element: the Unified Power Format, or UPF file. This is the latest standardized file format that allows you to specify your intentions with respect to power. Power domains, levels, gating, behaviors, and much more can be captured in one place and then be used throughout the entire toolchain. A single specification can drive synthesis and then be used as a benchmark for validation. So even if Synopsys had added no new capabilities, simply adding UPF support would have served to unify their offering from a power standpoint.

The breadth of power-awareness can be seen by the range of tools that now can take a UPF file as an input: their VCS simulator (with the MVSIM voltage-aware co-simulator); MVRC, a voltage-aware static checker; their Design Compiler, Power Compiler, and IC Compiler tools; their DFT MAX tool, which synthesizes a scan and compression scheme for testing; their Formality formal analysis tool, and their PrimeTime timing analysis tool.

Now, lest things seem too simple and cozy, if you’re not following the latest standards drama, you may not be aware that the UPF has an older rival. One contesting for primacy, protesting potential usurpation of title. Which is why I referred to UPF as “the latest” standard. But we’ll save the telling of that tale for another day.
OK… another Jack. That’s gonna raise some eyebrows, but fine… let’em sweat. Next: a 5. Hmmm… thanks for nuthin. But it’s ok, two cards to go, there’s still time… keep a cool head and a look of confidence, and perhaps get just a little luck…

Beyond UPF, Synopsys has focused this release on improving clock tree synthesis (CTS), automated power switch handling, and introducing power assertion into the validation suite. On the CTS side of things, prior approaches pretty much gave you the choice of a single clock gate that fanned out to many clock destinations, or many clock gates closer to the destinations. Their new approach is intended to provide better balance, optimizing skew, insertion delay, area, clock tree power, and total power. In addition, they have changed their placement algorithms to reduce the capacitance on nets with lots of activity and to cluster registers near their clock sources to reduce the length of clock lines. Shorter nets and lower capacitance of course mean lower dynamic power.

Power switching, as you may recall, involves dividing up the circuit into different power domains (which may or may not have the same voltage) and then allowing the power to be shut off in individual domains when not needed. While conceptually simple, this must be handled delicately. Where two domains meet, you have to be sure that no sneak paths turn on when one side or the other powers down. The power gates themselves must be big enough to avoid IR drops, but not so big as to waste space. The use of single big or multiple smaller power gates are all options, and placement matters.

Eclypse uses a two-step process to automate power switch synthesis. First it gives you a few roughed-out options, with estimates of power, area, number of switches, and the like. You pick one of the options, and it then automatically finishes the detailed implementation of that option.

OK, last up card… a king. That’s more like it. Don’t wanna get too excited here; don’t wanna scare anyone away. Nice and easy, ratchet up the bet ever so gently… two-pair is ok, but there’s another down card that could mean the difference between just ok and who’s-yer-daddy…

The third area of their focus is in verification: the ability to assert power. Simulation steps that allow you to turn on and off power for different voltage domains – whether or not gated – are intended to help isolate power bugs that may be hard to find otherwise. You can take the design through various power-up/power-down sequences and combinations to prove that the design is robust.

Synopsys has spent a lot of effort developing methodologies – as embodied in their Low Power Methodology Manual, in conjunction with ARM – and will be offering up that wisdom both for free and for fee. The free version is a  series of seminars, although you’d be best off traveling to one of the many locations in Asia if you’re not in one of the four northern North American sites (and I do mean northern: nothing south of Boston!) or the two UK cities on the itinerary. While it looks like the more traditional locations are getting short shrift, Synopsys actually says that they’re servicing those markets through their standard support arms, while focusing the seminars on areas that get less attention and where there is great demand for such seminars. Yeah, come on… before you pout and act all put-out and unloved, admit it… when was the last time you went to a seminar? I’ll bet you said, “I don’t have time to go to them. Let them come to me.” Am I right?

The for-fee part of the imparting of wisdom comes through services, of course. Honestly, the better the tools work and the more mature they get, the less design services will presumably be required (flawless tools must be a most frightening prospect for the manager of a design services group). But this is a rapidly evolving area, so I’m sure there’s room for everyone to get a piece of the action.

OK… here we go, last down card… “Jack or king… jack or king” he willed to the universe… His fate lay before him. He picked up the corner of the card and peeked…

Leave a Reply

featured blogs
Jun 21, 2018
Doing business today isn’t quite like it was back in the 80’s. Sparkling teeth and x-ray vision shouldn’t be a side effect of a customer using your product. This, of course, is said in jest, but no longer do we sell only a product; but a product and physical...
Jun 21, 2018
Welcome back to our series on cloud verification solutions. This is part two of a three-part blog'€”you can read part one here . The high-performance computing (HPC) market continues to grow. Analysts say that the HPC market will reach almost $11 billion by 2020'€”that'€...
Jun 7, 2018
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn'€™t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors '€” then progressing to gates, ALUs...
May 24, 2018
Amazon has apparently had an Echo hiccup of the sort that would give customers bad dreams. It sent a random conversation to a random contact. A couple had installed numerous Alexa-enabled devices in the home. At some point, they had a conversation '€“ as couples are wont to...
Apr 27, 2018
A sound constraint management design process helps to foster a correct-by-design approach, reduces time-to-market, and ultimately optimizes the design process'€”eliminating the undefined, error-prone methods of the past. Here are five questions to ask......