Since its introduction in 2005, SystemVerilog has been touted as the way to marry design and verification into a single language, enabling design with verification. Despite its blending of the best of Verilog, assertion languages and VHDL, SystemVerilog adoption has been slow — as with any new HDL or design methodology. But the language’s popularity is growing as tool support has improved, starting first with verification teams then expanding to ASIC designers and now also FPGA designers.
Why SystemVerilog in the First Place?
In times past, engineering teams would often throw their designs over the wall to test. Or course, design teams have long progressed past this stage, designing for test and cooperating with test organizations. But the hoped-for nirvana of design merging with test has not been reached, as tools, methodologies and languages have not merged. SystemVerilog is designed to bring us one step closer, allowing verification engineers and hardware designers to use the same HDL, keeping all in the design chain, well, speaking the same language.
Why is SystemVerilog not everywhere?
Engineers are a conservative lot — an if-it-ain’t-broke,-don’t-fix-it people. If they can get the job done with the tools and methodologies they have at hand, there is no reason to change. In fact, there are many reasons to not change: experience with tools and methodologies, comfort of working with proven technology, etc. Compounding this tendency has been the lack of comprehensive EDA tool support for SystemVerilog — it only takes one broken tool in the chain to convince a hardware designer that it is still too early for SystemVerilog.
What has Attracted Hardware Designers to SystemVerilog?
SystemVerilog has gained traction in the two areas that were the impetus for its development: verification and design. The attraction for verification engineers is obvious: access to an assertion-based language that is consistent with design, advanced testbench constructs, and seamless interface to foreign languages such as C and C++.Designer engineers are drawn to SystemVerilog because of its conciseness, readability, and higher level of abstraction with its support for user-defined and enumerated data types, plus C-like extensions. SystemVerilog also provides constructs to help in documenting and simulating design intent. Embedding this intent in the design source aids in design reuse and debug.
However, there is one aspect of SystemVerilog that is cited over and over again as one reason to move to this new HDL: the new interface construct. Rather than the error-prone, traditional method of having to copy and paste the large number of interface signals and the associated code to each block, an interface can be defined once, and easily called throughout the entire design with a simple construct. Gone are the days of changes in the interface having to be communicated to every designer and painstakingly edited into their code and testbenches.
The SystemVerilog Adoption Life Cycle
For engineers responsible for both verification and design, it made sense to use a single language; therefore, this group was the first to adopt SystemVerilog.
The next group to adopt SystemVerilog was ASIC designers not directly responsible for verification. Dealing with large, complex designs, these engineers were attracted by the ability to write cleaner and much more compact code that was easy to read. So the improvements found in SystemVerilog over Verilog (often achieved by importing concepts from VHDL) have made the lives of designers easier and have sped up the design and simulation task.
Quite naturally, once ASIC designers started to design with SystemVerilog, the next group to adopt the language were teams that were tasked with prototyping the ASIC designs using FPGAs. These teams were expected to use the same SystemVerilog code provided by the ASIC design engineers and to synthesize it into one or more FPGAs.
The last group to adopt SystemVerilog were FPGA Designers. As leading-edge FPGA designers have learned about the advantages of SystemVerilog form their ASIC and verification colleagues, they too have wanted to investigate this new HDL. However, early adopters have been hampered by the lack of complete support for the language throughout the entire tool chain, most notably in the area of FPGA synthesis. No matter how good an HDL is, it is useless unless it can be translated to gates.
Good News — Tool Support for complete FPGA Design is Available Today
Recent efforts by some EDA vendors have greatly improved SystemVerilog support, allowing early-adopters to gain access to all the features of SystemVerilog when doing FPGA designs. In addition to being able to simulate a design written in SystemVerilog, now it can be easily synthesized to target all FPGA architectures with a high quality of results. No wonder that increasing number of Industry-leading companies have begun to adopt SystemVerilog throughout their FPGA design teams.
SystemVerilog has helped take the industry towards an integrated design-with-verification methodology. But despite the emphasis of the language on verification, the language poses real power for hardware designers. As adoption grows within organizations, FPGA designers are feeling pressure from other departments in house (and from competition) to follow suit. And with vastly improved support by the FPGA synthesis and verification tool chain, the barriers to adoption have been lowered, giving FPGA designers access to the full power of the language. For many FPGA designers, it will soon be a question of whether to eat or be eaten!