feature article
Subscribe Now

New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support

In the past, physical synthesis tools for FPGA design were targeted to the advanced user and provided support for only a limited subset of devices. This has largely restricted the wide adoption of the technology. As a result, the Electronic Design Automation (EDA) tools have been inadequate in supporting the performance capabilities of the FPGA fabric. This article will examine the currently available FPGA physical synthesis tools and how a new generation of physical synthesis technology can help achieve timing closure faster, easier, and for a wider range of FPGA devices.

Why care about Physical Synthesis?

The move to smaller geometries such as 65nm has changed the rules of the game for FPGAs. In the past, cell delays used to be dominant and synthesis tools met the market needs by considering just these cell delays and wire load timing models in their algorithms. However, with the advent of the smaller geometries, routing delays have become a bigger challenge for achieving timing closure. EDA vendors and some FPGA vendors scrambled to address this problem with a variety of solutions. Previous solutions included post place-and-route (P&R) physical synthesis. With this solution, a user would synthesize and P&R the design before invoking the physical synthesis tool. Physical synthesis at that stage would use the real timing numbers reported by the P&R tool, and provide a complete view of the chip with the layout.  Advanced users would then have the ability to make changes to the physical location of specific blocks, create groupings of logic to lock them to a specific site, and start a series of physical optimizations to improve timing. A high quality physical synthesis tool would be smart enough to warn the user of illegal placements and groupings. Once this was done, the netlist would be sent back to P&R to complete the design iteration. When used effectively, this could yield timing improvement on critical paths and increase the overall Quality of Results (QoR) for the design.

What is needed to improve?

There are a variety of practical problems that have surfaced since the introduction of the first generation of physical synthesis tools. A big challenge is that an expert knowledge of the chip is needed to achieve significant performance improvement, and therefore, the use of physical synthesis is predominantly used by advanced users.  Most FPGA designers have small teams and do not have specialized groups focusing on each aspect of the design flow. Thus, a push-button, easy-to-use solution is not an option, but a requirement.

There are some push-button solutions available in the market today, which address the ease-of-use concern. However, they tend to operate in the pre-routing realm by performing physical optimizations and lock down the placements with an internally-developed detailed placer. This placed netlist is then passed to the FPGA vendor’s P&R tool for routing and bitstream generation.

A major challenge for this physical synthesis approach is that only a few FPGA devices are supported. This limits the designer to just a few devices which might not fit the requirements of the current or future design projects.  Since physical synthesis is important in today’s shrinking geometrics, a true vendor-independent tool should include physical synthesis that supports a broad range of FPGA devices.

Another common challenge of this approach is the lack of complete FPGA vendor design rule checks (DRC). As a result, customers using these tools might encounter DRC failures. The user is unable to debug the issue and is now at the mercy of the tool vendor to solve the bug problem.

In addition, this approach faces issues dealing with third-party intellectual property (IP). Typically, the IP is encrypted and the contents are not available to the synthesis tool. Therefore, the tool is unable to perform detailed placement and physical synthesis since this requires complete knowledge of the design. As a result, the designers are locked out from using these tools. To make things a little bit more interesting, FPGA vendors also offer some limited physical synthesis capabilities themselves. These FPGA vendor capabilities work well when operating on pure netlists, but not with synthesis solution which locks down placements.

Physical Synthesis for Everyone

The arguments so far have established the need for synthesis tools to be aware of the physical characteristics of the target FPGA device to produce the best QoR. A new state-of-the-art physical synthesis technology is necessary to address the challenges described above. This new approach must perform advanced delay estimation on the synthesized netlist, taking into account potential placements, available routing resources on the chip, and the design rules for the device. Armed with this information, the tool would perform a variety of physical optimizations such as retiming, replication, and re-synthesis.  This approach would help improve the overall timing of the netlist and can provide a much better starting point for P&R. Since the synthesis tool has much better timing models of the device, there would be no need to involve detailed P&R in the process, saving a lot of iteration time. This approach would be highly automated and would not require any involvement from the user. As a result, the technology could be used by all FPGA designers regardless of their expertise with synthesis tools.

The software architecture of this new physical synthesis technology must enable wide FPGA device support from all FPGA vendors and hence, provide designers with the flexibility to switch between FPGA devices as their project needs evolve. This approach would give the designer a true multi-vendor synthesis solution with the ability to select the best-suited device. If the FPGA vendor P&R tool offers physical synthesis capabilities of its own, the new physical synthesis technology would compliment it by providing a high quality netlist. In addition, the P&R runtimes would be shorter, due to the reduced effort required during this stage.

This approach would not lock placements or place other constraints on the P&R tool and allow P&R to achieve the best possible QoR. This clean “hand-off” between the new physical synthesis capability and the P&R would provide for optimized QoR, enabling designers to meet their project goals faster and with fewer iterations.

Leave a Reply

featured blogs
Aug 15, 2018
Yesterday was the first of two posts about Cadence Automotive Solutions. Today we go down into the details a bit more. However, there are so many details that this will be more of a map of the landscape so you get an idea of the breadth of our technology. Each item could have...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Aug 14, 2018
Introducing the culmination of months of handwork and collaboration. The Hitchhikers Guide to PCB Design is a play off the original Douglas Adams novel and contains over 100 pages of contains......
Aug 9, 2018
In July we rolled out several new content updates to the website, as well as a brand new streamlined checkout experience. We also made some updates to the recently released FSE locator tool to make it far easier to find your local Samtec FSE. Here are the major web updates fo...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...