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Cutting Costs with FPGAs

The age of big, expensive, power-hungry FPGAs is now officially over.  Of course, FPGA companies still make devices with three (and even four) digit price tags.  The biggest, baddest chips will probably be at that price point for awhile.  But don’t be deceived.  There’s a revolution afoot, and it isn’t at the high end.  The capabilities of low-cost FPGAs are where the real action is today.

There’s nothing new about low-cost FPGAs either, of course.  They’ve been around for close to a decade now, and the CPLDs that the earliest ones most closely resembled have been around even longer.  Those devices were just teasers, however.  The real revolution has been in the years that followed.  Low-cost FPGAs have gradually made their way up the density and capability curve and have finally developed some characteristics of their own that even high-end FPGAs can’t match.

The stakes in low-cost FPGAs are high because those cost-sensitive applications tend to be very high volume.  If you’re in the business of selling silicon, volume is the key.  Park one of your chips in a successful consumer or automotive application and you can watch the revenues roll in for years.  As a result, every FPGA company has attacked the emerging high-volume/low-cost segment with a vengeance.  This competition has had some interesting effects, bringing some significant capability down into the low-cost realm that might have otherwise taken years to migrate.

The two biggest FPGA companies – Xilinx and Altera, had the most to lose.  Each, on their own, probably would have taken a conservative approach to the low-cost line development, migrating only a few features into the low-cost versions of their devices to avoid cannibalizing or compromising the margin on their high-end chips.  However, with the war of one-upsmanship that has historically raged between those two companies, the stakes were quickly raised.  Each company carefully made their offering just enough bigger, faster, and more capable than the competitor’s previous product in an attempt to give themselves an edge, but not enough to steal too much thunder from the high-end devices that were their bread-and-butter. 

We’ve seen Altera’s Cyclone families and Xilinx’s Spartan families each go through three generations so far, each time with the bar being raised on density, performance, power consumption, hard-wired features, and I/O.  However, the battle really heated up when more vendors like Lattice Semiconductor and Actel entered the low-cost arena.  Those companies had nothing to lose on the high end because they didn’t have established high-end lines to protect.  They were free to play spoilers with innovative features that the big two were reluctant to roll into low-cost devices.  The result is a boon for designers with a wealth of capability coming into the low-cost chips.

First, the density and performance of low-cost devices has reached a really interesting level.  The first low-cost FPGAs were so small that most medium-complexity designs wouldn’t fit, but now Altera’s 65nm Cyclone III devices boast up to 120,000 logic elements (LEs).  That equals exactly 1.5 zillion system gates – enough to do almost anything.  Seriously, though – these LEs are 4-inpt LUT equivalents – so they don’t compare directly with the wider elements in the larger FPGAs.  The vendors tend to specify those in something like “equivalent LEs,” though – so you may not have too much trouble comparing.  Across vendors, it’s still almost impossible to compare density.  The vagaries of vendor-specific architectures give us everything from LEs to LUTs to “system gates” – none of which can readily be translated to real-world capabilities.

Regardless of how you count them, however, there are a lot of logic resources on today’s low-cost devices.  But, the story doesn’t end there.  There are even more interesting and exciting trends afoot that make low-cost FPGAs truly an enabling technology for discontinuous change in many high-volume applications.  It is in these areas that we’ll see the programmable logic landscape change over the coming years, and the products we create will change right along with it.

With the increase in low-cost FPGA density and the advent of practical soft-core processors, we got the ability to put full-blown embedded systems-on-chip into low-cost FPGAs.  In the current (90nm and 65nm) process generation, these system-on-chip capabilities go well beyond the simple applications possible in the past (a slow processor with a little bit of glue logic around it) enabling us to build full-fledged embedded systems – even sporting sophisticated RTOS or applications operating systems – on a low-cost FPGA platform.  Xilinx and Altera led the charge in this area with their proprietary MicroBlaze and Nios soft-core processor architectures.  Actel changed the game by partnering with ARM, the world’s largest processor IP company, to supply specialized versions of their popular ARM7 and new ARM Cortex M1 processors for use in Actel’s ProASIC and Fusion FPGA families.  Lattice Semiconductor took a different approach with their Mico32 soft-core which they made available through open source channels.

In order to support system-on-chip operation, you need more than processor cores and enough logic.  You need memory resources on-chip.  Available memory on low-cost FPGAs has also exploded.  Again, Altera’s 65nm Cyclone III currently leads the pack with as much as 4 Mbits of embedded memory on a low-cost FPGA.  With that much memory, you can accomplish a lot of work on-chip without having to go to off-chip memory.  Staying on-chip means lower total system cost, much higher bandwidth connection between memory and other on-chip resources (like hardware accelerators to compensate for the slow-ish soft-core processors), lower power consumption, and smaller board footprint – all major considerations for low-cost, high-volume applications.

Many devices such as Lattice’s XP and XP2 families and Actel’s ProASIC and Fusion devices also include a measure of on-chip non-volatile memory.  This storage is great for many security, DRM, and licensing applications, as keys and codes can be stored on the device in flash enabling a wide range of security measures for you as a product developer, for your customers, and for service providers that you may want to attract to your product platform. 

Since processing acceleration is one of the big things people want to do with FPGAs, and since DSP algorithms need a lot of processing, somebody early-on decided it would be a good idea to drop a few hard-wired multipliers on an FPGA – just for good measure.  Lattice Semiconductor came along and kicked that idea up a notch with full-blown DSP blocks, including multiply-accumulate functionality.  Again here, Altera’s Cyclone III leads the pack in numbers with up to 288 18X18 hardware multipliers that can run at up to 260MHz – If you do some rough marketing math, that gives you a (very) theoretical GMACs number somewhere north of 70 –  in a low-cost FPGA device.  The combination of DSP or multiplier blocks with an embedded processor allows you to use a very cheap soft-core processor (usually only pennies worth of FPGA logic) for most of your application and accelerate only the performance-critical sections in high-performance (but very power-efficient) logic.  The inclusion of DSP blocks also dramatically boosts the effective gate count of the device.

Actel added another dimension to the low-cost matrix when they introduced their Fusion devices.  These FPGAs combine a low-cost FPGA fabric with programmable analog blocks – enabling a wide spectrum of system control and microcontroller applications.  On-chip analog is (so far) unique to the Actel line.  Combined with the ARM processors, one can create a number of very interesting single-chip applications in these devices – again at a very low BOM cost, with a small footprint, and with very low power consumption.

Actel’s devices also started a trend in non-volatility as a value feature in low-cost FPGAs.  Since Actel’s devices use flash for their configuration logic, they are inherently non-volatile.  You can choose to build your system with a single chip and no configuration logic whatsoever on board.  Of course, if you plan to take advantage of in-system reconfigurability (which these devices support) you’ll still need some infrastructure to support that, but otherwise, non-volatility has some attractive benefits.  So many, in fact, that it brought imitators in the form of Lattice’s XP and XP2 families (architecturally different from Actel’s because they use more conventional SRAM fabric for the programmable logic, but incorporate on-chip flash memory for configuration).  Both approaches have technical merits, and the best choice for your application depends on which aspects of non-volatile FPGAs you were hoping to avail yourself of.  Not to be left out, Xilinx even introduced a non-volatile entry – by die stacking a conventional Spartan-3 device with a flash memory for configuration.  In our opinion, this was cheating a bit, but it does underscore the value the market puts on having a non-volatile offering in your lineup.

Of course, your design needs to talk to the outside world as well.  In the past, low-cost FPGAs offered only conventional I/O.  Again, Lattice Semiconductor played the spoiler by introducing a low-cost FPGA family with high-speed SerDes I/O – supporting PCI Express and Gigabit Ethernet.  This introduction sent the other vendors scurrying.  Altera introduced their own low-cost, SerDes-havin’ family “Arria” about a year later, and we wouldn’t be too surprised to see a Xilinx offering when they roll out a 65nm low-cost version of their Spartan line.

You couldn’t take advantage of any of this without proper tools and development kits.  While many design teams doing high-volume/low-cost designs are very sophisticated in their development environments and have invested in industrial-strength tools, it is possible to create a viable system-on-chip design on almost no budget whatsoever.  Many development kits are available for low triple-digit prices that include all the tools and hardware you need to get your creation up and running.  Third party vendors such as Altium are even bringing high-end vendor-independent design tools and development boards down to affordable prices.  With tools such as these, you can create your design, prototype it on development boards, and even go to limited production with COTS-type boards and modules with the right combination of features and plugs. 

Finally, there is a wealth of IP and reference designs becoming available for this latest generation of low-cost, high-performance FPGAs.  Using these jump-start capabilities, design teams can cut months from product development cycles.  Combining those benefits with BOM-friendly low-cost FPGAs can create significant competitive advantage over projects that follow other, more conventional paths, such as full-blown ASIC development, or waiting for exactly the right combination of ASSPs.

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