In the continuum of custom logic device technologies reaching from highly-custom Standard Cell ASIC at the high end to FPGA at the low end, we seldom hear from the node called “Embedded Arrays.” The extremes get lots of publicity. There is ample press and activity focused on both ASIC and FPGA, as these technologies are fairly easy to understand, and their benefits, problems, and trade-offs are quite familiar. The middle is a little fuzzier and (usually unjustifiably) frightens away analysts, press, and even development teams.
The “structured ASIC” flavor took a PR beating last year with LSI Logic’s rather visible retreat – cancelling their RapidChip product line. The move prompted other supporting vendors (such as Synplicity) to retreat from the technology as well. The combination of those events subsequently caused the press and analyst community to call the very idea of structured ASICs into question.
Structured ASICs have not gone away, however, with companies like ChipX, Altera, and others making a strong business from the technology. There is still a strong need in the market to fill the technology gap between FPGAs and ASICs with a noble compromise – something that fits in between the two extremes with higher density, higher performance, and lower power consumption than FPGAs can offer – combined with more flexibility, easier design, lower non-recurring engineering (NRE) and faster time-to-market than standard cell ASICs.
ChipX has just announced what they call “Embedded Arrays,” which are arguably a new step in-between traditional standard cell ASIC and structured ASICs. Embedded Arrays still use standard cell blocks for the performance-, power-, and area-critical parts of the design but have a gate array-like (sorry for using the now-forbidden “g” word) structure for custom logic and for easily creating variants on a basic platform.
The important thing to remember is that all these technologies are closely related. At a coarse level, all of them are silicon platforms that include some amount of pre-designed, highly customized IP, some amount of less-optimized IP, and some amount of custom logic and glue applied specifically for the target application. The only things that vary are the proportion of each and the technology used for integrating the custom logic.
In an FPGA, for example, the I/O blocks, memory blocks, hard-core processors, DSP blocks, and many other features are laid down with exactly the type of optimized hard-wired logic you would find in a standard-cell ASIC. FPGA companies have just pre-selected the most common “standard cells” and included them on the FPGA. They have to guess how many you’ll need, however. Any inaccuracy in that guess ends up costing you money, as you pay for any unused resources on your chip. The same holds true for structured ASIC – the manufacturer guesses how many I/Os, how many multipiers, how much RAM, etc. your application will require. You pay for the whole box of candy, even if you end up eating only the caramel ones.
Embedded arrays, although most similar to structured ASIC in concept, fall closer to the standard cell end of the spectrum. Both embedded arrays and structured ASICs provide a mixture of hard IP blocks and customizable, metal-programmable fabric. The difference is that in structured ASIC, the number and type of hard IP blocks has been pre-chosen and is integrated into the standard device. In embedded arrays, the hard IP is custom selected for your application. Unlike a full standard-cell design, however, there is also an ample supply of metal-customizable fabric that can be used to create variants, updates, and other low-cost alterations to the basic design.
If you’re in an industry like video displays, you could create your own standard-ish device that has the basic blocks common to all your product requirements. You could then use the programmable fabric to create the various product-specific versions required for the large number of feature sets and standards that your product line demands. The NRE for each version is much lower than for an entire standard cell re-spin. The design time is much shorter. The verification is much simpler, but the unit cost, performance, and power consumption are very close to the standard cell numbers.
ChipX’s new CX6500 Embedded Array family uses 130nm process technology and is based on the company’s previously available CX6000 structured ASIC fabric. ChipX has targeted high-performance, cost-sensitive applications with the new technology, including those needing newer interfaces such as PCI Express. Designs in areas such as WiMax, set-top boxes, DVRs, video players, PC add-on cards, and other media and media extension applications fit the sweet spot of heavy performance demands, low unit-cost requirements, and rapid evolution of standards.
ChipX says the new family is capable of integrating up to 8M true ASIC gates (don’t confuse these with FPGA “system gates”) and up to 10Mb of memory and 800 user I/O. I/O standards include LFCS, HSTL, SSTL, LVCMOS, and LVTTL. CX6500 can also integrate PCIe and other SerDes-based standards, including the PHY layer, USB 2.0 including the PHY layer, and a number of 3rd party ADCs and DACs. The company also has both 32-bit and 8-bit CPUs available for integration.
Compared with standard cell ASIC, the company says their NRE is approximately 70% lower, and the major re-spin lead time is 8-10 weeks versus 20-24 weeks typical of standard cell. The device cost is in the range of 20% higher than a corresponding standard cell design, and performance and power consumption are both within approximately 10% of corresponding standard cell numbers.
The tool chain for ChipX embedded arrays is identical to that for their other ASIC and structured ASIC products. HDL coding and simulation, synthesis, timing analysis, etc. are done in the traditional way, and handoff is at the RTL level for most designs.
With today’s crunched convergence demanding high performance, high density, low power consumption, low unit cost, and rapid turnaround with minimal NRE, embedded arrays offer a unique value point. Many design teams will be attracted to the attributes of ChipX’s new line, and the rich IP portfolio available will facilitate quick design times in a wide range of applications.