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Chip Estimate Fills the IP Gap

The race is on. Both competitors push pedals deliberately as the brakeless bikes start moving on the highly banked oval of the velodrome. Suddenly, before they have completed a second lap, the leader pulls his bike up the slope and comes almost to a stop, trying to lure his competitor into passing him on the inside. The duel that ensues is ironically typical of two-competitor sports like sprint cycling. Each cyclist strategically maneuvers his bike to try to gain the advantageous position – just behind the other in the aerodynamic wake. Sometimes, one of the cyclists will “track stand” his bike at a complete stop for what seems like an eternity (in reality, they can only hold still for a maximum of three minutes). Obviously, if there were more cyclists in the race, such a strategy would make no sense. The almost absurd approach is purely an artifact of the duopoly held by the two competitors.

For the two decades that FPGA design has existed, the methodologies have been following in the footsteps of ASIC design. As FPGA progress has accelerated and ASIC has stabilized, the gap has begun to close between the two design approaches so that it is often difficult to tell the difference between an FPGA and an ASIC design at many stages of the process.

One difference you could always count on, however, was that FPGA design would involve more of a one-stop shopping expedition. While a complete ASIC flow typically includes services, silicon, tools, and IP from a wide variety of suppliers, FPGA development has held fast to the “it’s all in the kit” philosophy. Most of this is due to the fact that the FPGA market is a duopoly, with two rival companies, Xilinx and Altera, together owning the vast majority of the market. In an effort to compete favorably with the other, each of the two companies regularly practice business in a way that would make no sense if they were competing with a larger field. Like a rider trying to win the race by deliberately stopping his bike, the two vendors pour millions of dollars into development of tools, IP, and capabilities that they never expect to sell for a profit. They seek only to gain advantage on the other in the two-competitor challenge.

The vendors will argue that all this strange strategy is ultimately in the best interest of the customer. Certainly, having all the tools and IP you need available almost for free from a single source makes the end user’s life very simple and keeps the cost of entry into FPGA design very low. In the longer term, however, it inhibits the growth of secondary markets like intellectual property (IP) for FPGAs. It takes a brave soul to build a business around FPGA IP with the knowledge that, on any day, one of the big FPGA vendors could start offering the same IP almost for free as part of their design kit. The result is a stifled IP market for FPGAs and a very limited selection of IP blocks available to the average FPGA designer.

Luckily, the situation is changing. The gate glut in FPGAs has made devices so large that IP-based design is the only reasonable way to productively populate them. The advantages of these devices are so compelling that they’re pulling into a wide variety of new markets. This sudden explosion of demand and breadth has created an IP vacuum that the FPGA vendors themselves cannot hope to satisfy. The participation of a broader IP development market is required in order to feed the beast.

A second factor helping to break the barrier is the use of FPGAs as ASIC verification platforms. It has become extremely popular in recent years to prototype complex ASIC designs in FPGAs. In order to accomplish this, your ASIC IP needs to be at least somewhat FPGA compatible. This has resulted in a trend of ASIC IP suppliers working to be sure that their IP cores work on popular FPGA families as well as on a variety of ASIC technologies.

The combination of these factors has created hope for a rich and robust market for FPGA IP after all. As in ASIC design, this creates a new (and welcome) challenge for the designer – browsing available cores from a number of sources and estimating the performance and resource impacts of a selected collection of IP blocks. As with many methodology improvements, the solution to this problem may come from the ASIC arena as well. Chip Estimate Corporation has come to the rescue with their combination of an IP catalog database and sophisticated estimation tools.

As more of your design becomes IP and less of it your own handwritten HDL, it becomes increasingly difficult to keep a handle on overall system specifications like chip area and performance. Chip Estimate has made a business in ASIC with their planning tools that help ASIC designers map out an IP plan for their system-on-chip designs. While these offerings may be a little rich for the average FPGA-based system design team, Chip Estimate’s new Chip Planning Portal may be just what the FPGA doctor ordered. “The idea behind the portal is to provide a mechanism to connect design teams with proven IP to plan their chip designs,” says Adam Traidman, President of Chip Estimate Corp. “Historically, we have focused primarily on SoC ASIC; however, with the launch of our chip planning portal, we now find ourselves catering to design teams using FPGAs and structured ASICs.” With a catalog of over 4,000 IP components, many which are compatible with FPGA implementations, Chip Estimate already allows designers to register for free and browse to find, say, IP that is compatible with a particular FPGA vendor or family.

If Chip Estimate’s IP selection and estimation technology catches on, there could be even better days ahead for FPGA designers – days when vast catalogs of IP can be easily searched and scanned for detailed information on the exact blocks you need to complete your design. Once you have your short list, you’ll want to get useful design-scale estimates like LUT count, amount and type of RAM consumed, speed grade requirements, power consumption, and I/O utilization.

Today, the economics of FPGA IP still block the potentially explosive growth possible in an FPGA IP market. Over the next few years, however, as the two key vendors inevitably loosen their death grip on FPGA IP availability and pricing, the boom in programmable logic IP will need a system to connect design teams with IP catalogs in a useful and organized way. When that day comes, our lives as designers will be different. Perhaps facilities like those offered by Chip Estimate will make that transition a little easier.

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