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Flash Freeze

Actel's Igloo Attacks Power

Actel’s new Igloo FPGA family is based on their popular flash-based ProASIC-3 line. In the world of FPGAs, flash offers some compelling benefits when it comes to power minimization. In developing Igloo, Actel has capitalized on those advantages and added new power management features, targeting the devices at extremely power-sensitive applications such as smart phones. While you may have never seen “mobile phone” and “FPGA” written on the same sheet of paper (unless there was a prominent negative in between), Actel seems determined to put FPGAs into these unlikeliest of sockets, attacking one of the last and strongest bastions of ASIC domination.

When talking about the power consumption characteristics of flash-based FPGAs, it is important to recognize that there are two significantly different programmable logic architectures that are labeled “flash FPGA.” Actel’s flash-based FPGAs use non-volatile flash for the actual configuration logic such as routing. Other “flash” FPGAs are actually more of a hybrid architecture: the configuration logic itself is volatile (SRAM-based), but the configuration data is stored on-chip in a flash memory. In those devices, the configuration is quickly loaded into the SRAM elements from the on-chip flash at startup.

When examining most properties of the flash-based FPGA (single chip operation, apparently non-volatile behavior, etc.), these two architectures appear almost identical. When discussing power consumption, however, there is an important difference. Actel’s approach has a distinct advantage in power consumption because the hybrid devices still require the volatile SRAM-based logic to be maintained with power just to keep the configuration active. Using Actel’s approach, the configuration is still active, even with power removed from the device. That means that there is no power spike each time the device configures itself and no constant drain of current to keep the configuration active.

In most power-sensitive FPGAs, power conservation is accomplished using external logic that puts the device into a “sleep” mode when it is not doing active work. In typical applications, the device is idle more than it is active, so the duty cycle is monitored and the device is hibernated and awakened at the appropriate times. For devices whose active configuration is volatile (SRAM FPGAs or SRAM/Flash hybrids) the configuration must be reloaded each time the device is awakened. This exacts a power penalty during restart in addition to the static penalty during active operation.

Because Actel’s Igloo device is statically configured, the options for low-power standby are much richer. First, Actel has added what they call a “flash freeze” pin. This drops the device into a low-power mode in 1µS. In this “flash freeze” mode, clocks are frozen, I/Os are tri-stated, and core registers and memories maintain state. In this mode, power consumption ranges from 5µW on the smallest (AGL030) device to 289µW on the largest (AGL3000E) device. This mode is similar to low-power states on many FPGAs, with the primary difference being that the flash freeze mode is simpler to execute and there is no current spike on wake-up because the device does not require re-configuration. Flash-freeze’s very low current draw should provide outstanding battery life in standby mode – a critical factor in most mobile devices.

The second power saving mode (unique to Igloo) is a “low-power active” mode. This mode is quite interesting because it comes along essentially for free. All you need to do to use this mode is to stop clocking the device (or dramatically slow the clock, if you’re doing a sequential low-power monitoring function). In this mode, the device can actually be used as the alarm clock for the system, monitoring signals and issuing the wake-up call for system components to come back from low-power standby. Low-power active mode consumes more power than flash freeze – ranging from 24µW for the smallest device to 333µW in the largest.

In order to reduce dynamic power consumption, Actel has lowered the core voltage for Igloo to 1.2V. For battery-powered applications, this is ideal, further separating Igloo from competitive low-power FPGAs and CPLDs. The tradeoff, of course, is performance as the core delivers lower Fmax at the lower voltage.

Overall, Igloo should occupy a unique position in the low-power programmable market. Compared with other similar offerings, it has higher available density, ranging as high as 3-million marketing (oh, sorry, “system” gates), and offers a host of FPGA-like capabilities that separate it from most common CPLDs. When compared with antifuse-style non-volatile devices, it offers in-system reprogrammability, which could be a key advantage in fast time-to-market mobile devices. It also offers a lower power-per-effective–gate-per-megahertz than any competitive device we’ve reviewed, and its low-power and standby modes are unique offerings at this point.

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