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Altera’s Quartus II 6.0

Tools Turn up the Heat

The FPGA market is a multi-faceted battlefield. Particularly between the largest two suppliers, everything is a race. There is a race to reach a new process node first, a race for the largest device, a race for the highest frequency, and a race for the lowest-cost parts. Silicon-based bragging rights aren’t enough to keep the conflict interesting, however. Both Altera and Xilinx, the two market-dominant FPGA suppliers, invest huge amounts of resources in the development of tools and IP to complement their device offerings.

While not as visible as the war of the wafers, the contest to provide the most powerful, easiest-to-use, most broadly applicable tool suites at the lowest cost to their customers is a hard-fought battle. Recently, Altera announced their latest salvo in that conflict with the introduction of their newly-enhanced Quartus II 6.0 design tool suite for Altera FPGAs and CPLDs.

Altera’s new Quartus 6.0 brings two headliner enhancements to the table that the company believes will benefit designers today in their 90nm designs, as well as in future designs at 65nm and below. The first is a new, ASIC-strength timing analyzer that the company has dubbed “TimeQuest.” The second is a new project manager interface designed to improve team-based design of FPGAs. Both enhancements reflect the continued push of FPGAs into higher realms of design complexity and the corresponding need for more grown-up tools to support that design. Altera’s decision to pursue these and other recent tool projects on their own rather than by partnering with third-party EDA companies also indicates a shift in strategy differentiation between Altera and their number one nemesis Xilinx.

Over the past several years, all but the most pedestrian FPGAs have reached a level of timing complexity that old FPGA tools simply cannot comprehend. Multiple clock domains, complicated timing requirements, and the migration of ASIC designs onto FPGAs for prototyping and early production have popped the buttons off traditional FPGA tools like Bruce Banner’s wardrobe in a fit of rage. In order to handle this timing complexity, third party EDA suppliers like Synplicity and Mentor Graphics bolted ASIC-style timing engines onto their synthesis tools several years ago. In addition to higher performance and capacity, these timing engines allow much more sophisticated and precise specification of timing constraints through their robust constraint languages.

One problem with third-party EDA-supplied FPGA synthesis tools supporting sophisticated timing is the inevitable impedance mismatch when coupling those tools to the FPGA vendors’ timing engines built into place-and-route. First, the EDA company tools use constraint languages like Synopsys Design Constraint (SDC) or Synplicity Design Constraint (um, also “SDC” – no relation) as the primary mechanism for the designer to specify the required timing relationships for their design.

After synthesis, both the design and the timing constraints have to be passed from the synthesis tool downstream to the FPGA vendor’s place-and-route software. In the case of timing constraints, this usually means not only a syntax translation, but also a semantic re-interpretation of those constraints into a less sophisticated model for consumption by the place-and-route tool. The result is often timing results that are confusing to the designer, since the re-interpreted constraints may look unfamiliar to the designer who is slogging through timing reports from the place-and-route tool.

Now, Altera is moving to an industry-standard model provided by Synopsys Design Constraints (SDC). (Actually, their tools are now dual-mode, supporting both SDC and their legacy timing constraint language for backward compatibility.) The benefits of SDC support include a consistent semantic and syntactic specification and interpretation of timing constraint information throughout the tool flow and a huge advantage in familiarity by the thousands of designers already schooled in the Synopsys constraint format.

This top-to-bottom consistency will pay dividends for design teams using FPGAs for ASIC prototyping (as their designs can now be ported between ASIC and FPGA environments more smoothly) as well as for design teams working on highly-sophisticated FPGA-only projects using later-generation (90nm and beyond) FPGAs.

On the third-party scene, Mentor Graphics Precision synthesis tools have supported Synopsys SDC from their inception, and Synplicity is in the process of adding Synopsys SDC support to their already-popular Synplicity SDC in an upcoming version. Altera emphasizes that their SDC support is native, meaning they implement SDC directly instead of simply translating from SDC to a different internally-supported format. This lack of translation should translate into increased compatibility between various tools that support SDC from Altera as well as from third-party vendors.

In addition to requiring more sophisticated timing analysis, the larger designs allowed by today’s FPGAs demand more of another commodity – designers. We have now moved well beyond the time when most FPGA projects can be handled by a single designer. Our own FPGA market studies show that the average FPGA design team is somewhere between 2 and 3 today, with peaks in the distribution at 1 (for people doing smaller designs) and 4 for people tackling more sophisticated FPGAs.

Handling a multi-engineer project with tools designed for a single engineer can be challenging, and Altera has recognized that challenge by adding improved team-based design features to Quartus. The project manager interface in Quartus II version 6 facilitates partitioning of the design into separate segments and manages the resource and timing budgets at the top level. The management of constraints between blocks allows individual designers to work independently on their segment of the design while maintaining compatibility with the work of the rest of the team and with third-party IP that might be included.

Because team design is frequently somewhat asynchronous (one designer may be almost finished with his block when another is just starting), the incremental capabilities of the team-design feature allow for one designer to get timing closure on his block without later having that work disrupted by another designer’s block being merged in. Making all this work requires that the synthesis and place-and-route tools support some level of incremental compilation (which Altera dropped into Quartus in a previous release) and that the place-and-route tools honor previous placements of blocks that have already been closed. Altera’s previously announced “LogicLock” works behind the scenes to preserve placements during team-based incremental design.

Also new in the Quartus 6.0 package are an initial round of SystemVerilog support, an improved pin planner allowing easier integration of IP and simpler pin assignments, HSPICE models of design outputs for Stratix II to help board-level design analysis, and incremental improvements to both the SignalTap embedded logic analyzer and the aforementioned LogicLock. While no new power optimization or analysis features were specifically tied to this release of Quartus, power reduction is clearly a priority with Altera, based both on the enhancements to other recent version of Quartus and on the ambitious power-mitigation strategies recently disclosed for their upcoming 65nm FPGA families. [read related article]

These changes represent a more aggressive internal tool development face than we’ve seen in recent years from Altera. Taken together with Altera’s recent announcement of their own C-to-FPGA algorithmic synthesis capability (C2H) they appear to signal a more “go it alone” tool strategy from the company, ironically at the same time that rival Xilinx appears to be opening up more to partnerships with third-party tool suppliers.

For FPGA companies, tools and IP are coming to a juncture of criticality on competitive strategy. First, FPGA vendors had to provide their own tool suites directly to customers as enablers of FPGA-based design. Later, FPGA vendors chose to enhance those tool suites in order to gain competitive advantage. Once tools and IP became a competitive differentiator between FPGA vendors, neither of the two large FPGA companies wanted to “blink first” and charge more for their tools or reduce their tool development efforts. This standoff stifled third-party tool development, keeping the market down to just a handful of hardy, steel-willed suppliers like Synplicity, Mentor Graphics, and Altium.

Today, as a result, FPGA companies are faced with two problems. First, continuing to pour ever-increasing sums into design tool development without direct corresponding revenue raises their cost structure and opens the door for competitive solutions. Second, as FPGAs find their way into an ever-broadening role in system design, the number and diversity of tools and IP required to satisfy those markets becomes exponentially larger, demanding a huge increase in tool and IP development.

FPGA companies, primarily Altera and Xilinx, now have to make careful decisions about which tool capabilities and IP they offer directly and which ones they provide to their customers through third-party partnerships. If they follow the “we can do everything ourselves” strategy, they are ultimately doomed to failure as they try to take on internal development projects of epic proportions for essentially non-revenue-generating products. By offering these products at artificially low prices (often free) they also suppress the growth of any third-party tool and IP market that might free them from that development burden. Eventually, though, this provides an excellent opportunity for smaller vendors such as Actel and Lattice to partner with third parties and offer similar or even possibly superior capabilities at much lower cost to them.

If, on the other hand, either of the two largest vendors backs off of their own development first, they risk giving up market share if their competitor can create a temporary advantage with proprietary tools and IP. Recently, with Xilinx making more noises about partnerships and “ecosystems” and Altera apparently stepping up their own internal development, the two may be testing the waters on opposite sides of that problem.

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