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Ask for Whom the Bell Tolls

RapidChip, or Structured ASIC?

I was at DATE 2006, a tradeshow in Germany. My cell phone started buzzing with calls, voicemails and e-mail. People were stopping me on the show floor – pulling me aside, whispering rapidfire questions – always small variations on a theme. “Did you hear that LSI Logic is killing RapidChip? Do you think that structured ASIC is dead? Are other structured ASIC vendors pulling out as well? Will FPGAs wipe out the structured and platform ASIC space entirely? What’s Altera doing? What about ChipX? Isn’t AMI doing structured as well? Has eASIC been acquired yet? What have you heard from Fujitsu?”

Hey! I’m supposed to be asking the questions here.

The announcement had just hit the wire. LSI Logic was discontinuing (or de-emphasizing) the RapidChip family. The company would now focus its resources on the consumer and storage markets.

For a little background, LSI Logic’s RapidChip family was one of the most successful and capable structured-ASIC offerings on the market. The company was obviously dead serious about the product line, having invested several years of intensive engineering and marketing effort in the project. The phrase “betting the company” had been bantered about in analyst and editorial circles. The common theory had been that LSI Logic had long been closely tied to the cell-based ASIC market, and that market was on a sustained decline. Structured and platform ASIC represented new hope – a market where rapid growth was forecast, rather than ASIC’s long, painful demise in the face of increasing (and already staggering) development costs.

Structured ASIC presents an interesting question for the EDA industry as well. Before structured ASIC, EDA had two places it could invest in the development of chip design software – ASIC and FPGA. FPGA design has always been dominated by tools supplied (almost for free) by the FPGA vendors themselves. That makes FPGA a tough market for third-party EDA because they’re always at risk of investing tremendous resources in the development and marketing of FPGA design tools, only to end up competing with free or heavily subsidized offerings from the FPGA vendors themselves. Additionally, FPGA design is fairly easy to learn, and there is a low cost associated with tool transition. All this makes EDA executives extremely reluctant to dive headlong into the FPGA tools market.

ASIC design, on the other hand, has been dominated by third-party tools for decades. Designers are willing to pay top dollar (and much more than top dollar in many cases) for ASIC tools because of the incredible cost of an ASIC re-spin. Even the most aggressively priced verification tool can earn its keep in a single run if it helps to avoid an ASIC re-spin, with its associated cost overruns and schedule delays. Unfortunately, ASIC has a severe downside for EDA as well. The number of ASIC designs has been steadily decreasing for years, and the cost and complexity of the tools has been steadily increasing with each subsequent process generation. EDA could be left building more and more expensive tools for fewer and fewer customers – not a pretty scenario for growth.

Structured ASIC, however, has the potential to carve a happy groove between those two unhappy extremes for EDA. Structured ASIC vendors don’t seem particularly interested in being a one-stop shop for tools and silicon as the leading FPGA vendors do, and there is at least some NRE and schedule cost for a re-spin that lets EDA do that good old fear-based marketing that EDA knows and loves. “Want to avoid costly and career-limiting ASIC re-spins? Just use our super-XYZ-zapper and your job is safe and secure.”

Probably the most visible and aggressive EDA vendors in exploring the structured ASIC opportunity have been Synplicity and Magma Design Automation. Banking on the carry-over of FPGA-like methodologies into the structured ASIC business, Synplicity jumped on the train early, before it even left the factory. Synplicity developed synthesis capabilities for most of the active structured-ASIC offerings and crafted a vendor-specific business model that protected them from FPGA-like product devaluation while keeping the marketing and distribution overhead to a minimum. Magma has approached structured from the ASIC side, applying their techniques and technology from ASIC in specially adapted ways to serve the emerging market. Both companies stand strong in their commitment to structured ASIC despite the LSI Logic pullout.

So – what does LSI’s retreat mean? Is there some inherent weakness in the structured ASIC philosophy that makes it an unviable strategy? Is there less gap between FPGA and ASIC than we all imagined, allowing one solution or the other to always capture the business, and leaving structured in the cold?

Our answer to these questions is an emphatic “no.” The reasons behind LSI’s strategy shift are complex and somewhat company-specific. No company can do everything at once and do it well, and smart executives know how and when to focus their company’s energies on the projects that will bring the most return and growth and that capitalize on the organization’s unique strengths. LSI had good momentum and competence in the storage and consumer markets, and those made sense as a place to focus the company’s remaining resources in a difficult business situation.

The part of the situation that isn’t company specific is the orthogonal trend toward domain-specific optimization of silicon platforms. This specialization can be seen across industries and across silicon technologies. With the exception of full-blown ASIC, every customizable silicon technology makes some serious technical compromises. For FPGAs, these compromises are obvious in the LUT fabric which gives away an order of magnitude or so in speed, density, and power consumption for the privilege of reprogrammability. In structured ASIC and in non-volatile FPGA technologies like antifuse, the configurable fabric penalty is smaller, but still significant. Every vendor’s solution to this problem is the same – create ASIC-like hard IP blocks for critical functions.

Hard IP can take large, performance-critical hardware, like multipliers, memory, and high-speed I/O standards, and implement them much more efficiently than a designer attempting to put that same capability in the programmable or customizable part. This gain comes at a cost, however. Every customer that doesn’t use a particular function that is hard-wired on the chip is essentially paying for wasted silicon. The juggling act for semiconductor companies, therefore, is to decide which functions (and how many) should be hardened in order to give the best mix of performance and cost optimization. For example, if your customers are doing high-speed digital signal processing (DSP), it probably pays to put a number of hard-wired multipliers on your chip. Even then, however, the question of “how many” poses a challenge. Do you need ten? A hundred? A thousand? The particular application area determines the answer.

In fact, the particular application area determines the answer for most of the hard-IP related questions. If you are a silicon vendor, and you know something about what your customers will be designing, you can do a much more effective job picking which functions to harden, giving you a substantial advantage over a competitor trying to market a truly general-purpose chip. Silicon vendors realize this, of course, and there is now an increasing trend toward market-specific customizations of silicon platforms and away from completely generic devices. Even high-end FPGAs, some of the most versatile general-purpose devices in the world, are moving toward increased domain specificity. Xilinx and Altera both offer different versions of their high-end families with varying hard-IP mixes aimed at attracting various types of applications.

FPGA companies like QuickLogic have taken the idea to even more of an extreme, providing very domain-specific mixtures of IP with programmable fabric blended in to allow just the amount of customization those industries might require. For a designer, the net result is that you’re probably best served by going after the product that is the most specialized toward what you’re doing. If you’re developing a disk controller for a handheld device, and there’s a ready-made ASSP that does the job exactly, use that one. It will probably give you the best performance with the lowest cost of development and deployment. If not, you might find a chip that has almost the right capability in hard IP, with enough customizability to make it do your job. Failing that, you might fall back to a more generic and even more customizable option (which will probably cost more, take more time to design/deploy, and perform worse.)

For structured ASIC, these same principles apply. RapidChip is/was a fairly generic platform. As such, it didn’t have the richness of domain-specific hard IP that one might want for a near-ASSP solution. You’d have to develop a lot of capability yourself using the (ample) customizable fabric. While this doesn’t extract the same penalty as using FPGA fabric, it does achieve some of the same negative result in market performance of the platform. Ready-made functions are very attractive to designers.

On top of the domain-specificity of IP, however, is the focus of marketing and sales. If you’re selling a chipset or customizable silicon platform for, say, WiFi implementation, you can hone your marketing messages and focus your sales efforts much more effectively and efficiently than somebody marketing a one-chip-fits-all silicon platform solution that happens to also support WiFi. Your semiconductor sales and marketing can speak the customer’s own language rather than forcing the customer to learn to adapt your world to his.

These effects can be seen clearly in the LSI Logic refocusing as well. By going after the consumer and storage markets, LSI can fine-tune their messaging and marketing efforts, getting much more efficient traction with their targeted customer base. It’s a sound strategy.

For the nascent structured-ASIC market, however, watch for more innovation, consolidation, success and failure in the near future. New technologies don’t grow in the market in smooth, orderly ways. Every semiconductor vendor we contacted for this story was emphatic about the validity of their structured ASIC strategy. Of course, each one is different. Altera, for example, may be doing more structured ASIC business than anybody with their HardCopy line. Structured ASIC as a simple cost reduction from a working FPGA design is a compelling value proposition for a number of customers. AMI, in fact, has made a company and a career for years based on that same philosophy.

On another front, ChipX is working the domain-specific angle, gaining their advantage by moving structured ASIC solutions into specific target markets with just the right mix of features and capabilities. There are also rumors of a number of startup semiconductor companies deploying similar strategies with either FPGA- or structured ASIC-like programmable fabrics allowing deep customization of domain-specific chips. And in yet another direction, companies like eASIC are bringing new technologies to bear that change the rules for customization, NREs, and minimum volumes.

All of these companies can make strong technical arguments for their strategies. Most extend those arguments into business cases for choosing their silicon platform over another. Beyond that, however, as we see in the case of LSI Logic and RapidChip, the health and focus of the semiconductor company as a whole is a strong factor in the longevity of any product offering. Today, the bell tolls for RapidChip. We will all miss it.

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