feature article
Subscribe Now

Think You Know Where Structured ASICs Belong?

Over the past couple of years, the notion of Structured ASIC and Platform ASIC architectures, let’s refer to both as Structured ASICs, have received a lot of attention from the chip industry. Structured ASIC proponents tout the concept as a way of getting near-ASIC performance and unit pricing without the high NREs and long and complex design cycles of ASICs. On the other side, skeptics dismiss Structured ASICs as a ploy to save what they consider to be a dying ASIC design industry. In reality, the benefits of Structured ASICs lies somewhere between these two viewpoints – exactly where depends from where you are looking.

The Trouble with ASICs

Yes, ASICs done with a traditional business model and methodology are expensive. NRE costs are projected to be $20M and up for chips designed at 90nm. They are also risky, with low cost- and design-time predictability along with relatively low reliability of first-time silicon success in the chip’s target system. So, why do companies take on ASIC designs? They develop ASICs because they offer the lowest unit cost and highest performance of any silicon platform. The financial and design-time resources that cost so much means that the chip’s design team can optimize the final chip for the most desirable tradeoff of chip area, speed and power.

The cost, predictability and reliability problems associated with ASICs are also associated with traditional ASIC development models. In reality, ASICs comprise three categories of chips (Figure 1):

1. Low-End—These are low-complexity designs that are targeted for low-volume applications. FPGAs have successfully overtaken the low-end ASIC application space and are impinging on the mid-range space as prices drop and performance rises.

2. Mid-Range—This is the ASIC “sweet spot,” around 80% of all ASIC design starts. ASICs in the sweet spot range from as low as 100K up to 12M gates, with up to 15Mbits of memory, and are implemented at main-stream process nodes, currently 180nm down to 90nm. Core speed at 90nm nm goes up to 500 MHz. These ASICs can be designed using a fixed design methodology or “design factory” approach.

3. High-End—This category comprises very complex and high-performance ASICs. Cost is relatively unimportant for implementing high-end ASICs (so-called “success at any cost”). There is no fixed design methodology for high-end ASICs and each chip requires some level of design-methodology customization. As process nodes shrink, the level of customization and the NRE goes up, way up.

20060228_open_fig1.gif

Figure 1. ASICs comprise three separate regions, each with its own complexity, performance and
cost characteristics. The position of Structured ASICs on this curve within the mid-complexity
region is different for FPGA, traditional ASIC and “design factory” ASIC vendors.

By their low-complexity nature, low-end ASICs have a high level of reliability and predictability and are relatively inexpensive to design. Using a “design factory” approach, mid-range ASICs can be designed with significantly better reliability and predictability than if they were designed using traditional design approaches, and at a much lower NRE cost. High-end and mid-range ASICs developed with traditional design methodologies are the reason why the industry perceives ASICs as being expensive to design and has led to the decline of ASIC design starts over the past several years. This decline is due to two factors: the spiraling increase of ASIC NREs and the effects of increasing chip density, and hence functionality, allowing a single chip to do a job that use to require two or more chips.

Structured ASICs from an FPGA Viewpoint

From an FPGA point-of-view, a Structured ASIC would appear to be a version of a traditional ASIC with only a few differences. A regular ASIC has its complete functionality defined for a specific customer, thus defining all the process layers that comprise the chip. Once out of fabrication, an ASIC cannot change what it does except through software, such as defining the tasks that a DSP or RISC core would perform. As the chip has one customer, the development cost to that customer is very high due to the complexity of the chip’s development. The cost of a full mask set for processing the chip is also high, a million dollars or more for a 90nm chip, but this represents less than 10% of the total development cost. The design effort needed to develop an ASIC is the high-cost culprit.

A Structured ASIC, on the other hand, has most of the mask layers defined for and the processing done up to a subset of the full process and then the chip is banked for future customizing. Functions such as I/Os, clock networks, memory and other IP are defined for that particular silicon platform. The remaining process steps, metal and via definition, “personalize” the chip for a particular customer and application. This allows the “common” development and processing cost to be amortized among the various customers of the Structured ASIC chip, reducing the overall cost compared to that of an ASIC. Structured ASIC customers benefit from lower NRE costs and shorter development cycles (most of the chip has been pre-designed and pre-verified). The downside is that performance is lower than what you can get from an ASIC with the same functionality and unit cost is higher. Design risk is still high, however, and needed silicon re-spins if the chip doesn’t work can significantly eat into the initial cost and development time savings.

FPGA vendors look at Structured ASICs as a stopgap measure to make cell-based designs available to those chip vendors who cannot afford the high development cost and often unacceptable risk and reliability associated with full ASIC designs. When comparing Structured ASICs to their own products, these vendors see Structured ASICs as still very expensive to design, with longer design times and much higher NREs, and inflexible, since the hardware on a Structured ASIC chip, like an ASIC, is fixed upon completion of wafer processing. Performance is below and unit cost is above what can be obtained with a traditional ASIC, but both are improvements over what FPGAs can do. This makes the Structured ASIC a good alternative to an ASIC for some mid-range complexity designs with volumes that are in the 10K to-100K range. FPGA vendors are feeling pressure from Structured ASICs as FPGAs try to gain market share in the mid-range ASIC category.

One leading FPGA vendor has acknowledged the value of a Structured ASIC product with its own Structured ASIC solution. This allows their customers to validate a design with an FPGA and then migrate to a Structured ASIC for significant cost reduction over the FPGA. Again, this strategy is under the same design-complexity constraints as are other Structured ASICs.

Summarizing, to the FPGA vendor a Structured ASIC is another type of ASIC – a mask-programmable, cell-based chip – that belongs near the top of the mid-range ASIC complexity curve. Anything below that point can be handled, complexity-wise, by an FPGA and, unless volumes are really high, FPGAs are more cost-effective as well.

Looking from the Traditional ASIC Side

For the highest performance and lowest unit cost, ASICs are still the chips of choice, albeit with risk and development cost hits. Up-front cost is so high, however, that only designs that expect to see very high volumes and revenues should be done through a traditional ASIC approach. Structured ASICs fit below the high-end ASIC category, where the extra unit cost and reduced performance are acceptable. The mid-range area is one from which traditional ASIC vendors are backing away – the ROIs often don’t warrant the risk and expense of a traditional ASIC. To a traditional ASIC vendor, the Structured ASIC appears as a lower end ASIC alternative, nearer to the middle of the mid-range region of the complexity curve of Figure 1.

The “Non-Traditional” ASIC View

Another category of ASIC vendor has appeared, one who views Structured ASICs further to the left on the complexity axis of Figure 1 than does the traditional ASIC vendor. This “open-model fabless” ASIC vendor combines extensive design and product engineering expertise with customer-driven supply-chain implementation. The vendor applies a “design factory” model to design-chain activities and an aggregation model to the supply-chain to produce ASICs that are less expensive, more reliable and more predictable in terms of cost and schedule than those that a traditional ASIC vendor can turn out.

By using a design factory approach to chip design activities, the open-model fabless ASIC vendor targets mid-range complexity ASIC designs that do not need the custom approach required for high-complexity ASIC chips. With this constraint, the vendor can use a common set of design tools and design platforms, along with a common design methodology, to create chip chips that require much fewer design resources than do chips developed by the traditional ASIC vendor. This results in NREs significantly lower than those of the traditional vendor as well as chip with a much higher probability of first-time silicon success.

Also unlike a traditional ASIC vendor, this new breed of ASIC vendor, with aggregation of supply-chain activities, enables customers to be part of all supply-chain choices – fabrication, assembly and test. This not only reduces cost through economies of scale and accelerates chip manufacturing throughput, but it also reduces risk throughout the supply-chain operations due to the expertise of the ASIC vendor.

To the open-model fabless ASIC vendor, Structured ASICs belong where they are shown on Figure 1 – at the bottom of the mid-complexity region. All ASICs of higher complexity, but still in “mid-range,” this type of ASIC vendor can handle, since he can offer customers much lower design costs and more predictable and reliable chips that are still true ASICs without the inherent loss of density and performance associate with Structured ASICs.

It All Depends on Where You Are

All three chip vendors – FPGA, traditional ASIC, and open-model fabless ASIC – agree on what comprises a Structured ASIC. The disagreement comes about in determining when to implement a Structured ASIC as the silicon platform for a design. Each faction’s positioning of Structured ASICs is colored by their idea of their own chip design and manufacturing capabilities and costs. The only agreement is that Structured ASICs belong somewhere “in the middle” of complexity and volume requirements, between traditional ASICs and FPGAs. The problem is that “the middle” is a big area and each vendor wants to maximize the market addressed by his technology and business model. So…there is a place for Structured ASICs, just no agreement as to where, exactly, this place is between high-end ASICs and FPGAs.

Leave a Reply

featured blogs
Jun 21, 2018
Doing business today isn’t quite like it was back in the 80’s. Sparkling teeth and x-ray vision shouldn’t be a side effect of a customer using your product. This, of course, is said in jest, but no longer do we sell only a product; but a product and physical...
Jun 21, 2018
Welcome back to our series on cloud verification solutions. This is part two of a three-part blog'€”you can read part one here . The high-performance computing (HPC) market continues to grow. Analysts say that the HPC market will reach almost $11 billion by 2020'€”that'€...
Jun 7, 2018
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn'€™t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors '€” then progressing to gates, ALUs...
May 24, 2018
Amazon has apparently had an Echo hiccup of the sort that would give customers bad dreams. It sent a random conversation to a random contact. A couple had installed numerous Alexa-enabled devices in the home. At some point, they had a conversation '€“ as couples are wont to...
Apr 27, 2018
A sound constraint management design process helps to foster a correct-by-design approach, reduces time-to-market, and ultimately optimizes the design process'€”eliminating the undefined, error-prone methods of the past. Here are five questions to ask......