feature article
Subscribe Now

Planning Ahead

Xilinx Updates Hierarchical Design Tool

It’s a cold February morning in a well-hidden corner of Silicon Valley. The air is perfectly still. The sun is just rising above the hills, although it isn’t clearly visible through the dissipating ground fog cast over the region by the bay. There is a light frost on the grass, even though the temperature has been in the 40s all night. That’s one of the big issues with fictional, metaphoric introductions to technical articles – continuity problems. These things clearly would never stand up to an engineering design review.

Any moment now, Silicon Valley Stan, the timing-closure groundhog, will emerge from his burrow. He’ll whip out his smart-phone, maybe check the stock reports, listen to a couple of voicemails from his boss about the embedded software project falling behind schedule, start downloading his daily podcasts, and then step out of the threshold into the light. This, of course, is the moment of truth. If the angles and locations are just right, if the sun has penetrated the fog, if the route he follows on his way to work happens to follow just the right path – he may see his shadow. If he does, we’ll have six more weeks of timing-closure problems, iterations through synthesis and place-and-route, changing RTL and constraints, moving I/O locations – all in a futile bid to foil the random hand of fate.

Sounds pretty arbitrary, doesn’t it? Have you ever had timing violations on an FPGA design? Frequently, they seem to make just about that much sense. You start with the ominous timing report with a couple of paths showing negative slack. You make a tweak or two, perhaps re-run synthesis with different options, and things start to look good. The next day, the guy down the hall changes some trivial part of the design that’s miles from anything you’ve worked on, and suddenly chaos begins. Your part of the design no longer meets timing. You change a few more options and end up with more violations instead of fewer. The other guy’s section of the design still works fine, of course, but now your problems are bleeding into other parts of the process. You had to move some I/Os around, and now the board design folks are angry. Things snowball until, for no apparent reason, you’re the one on the critical path of the project schedule. It’s time to forget about weekends and start skipping the kids’ soccer games. The timing closure groundhog has spoken.

Xilinx has just released an improved version (8.1) of their PlanAhead tools, acquired from Hier Design a couple of years ago. When properly used, PlanAhead can act as gopher mesh to ward off the timing closure groundhog and to keep a lot of the other aspects of your complex FPGA design on track. Strictly speaking, we’d have to call PlanAhead a floorplanner, although if you start off thinking about floorplanning, you’re likely to miss most of the practical elegance of this tool. While Xilinx’s news release curiously proclaims “Two Speed Grade Advantage over Competing Solutions,” we’d be inclined to argue that there really are no competing solutions. PlanAhead has always taken a unique approach to design planning that, although many tools share some of its features, gives it a singular place in the solution space.

PlanAhead is an extra-cost option available from Xilinx with their ISE toolkit. According to the company, 2005 has been a banner year for the product, with a 50X increase in registrations and a steep growth ramp throughout the year. The reason designers are flocking to the tool is the capability it offers to analyze and visualize a design after synthesis and to add additional constraints that help to insure success after place and route – in other words, floorplanning.

With increasing densities, decreasing feature sizes, and more complex clocking, the timing closure groundhog has been visiting FPGA designers much more frequently with the latest generation of devices. Routing delay has increased as a percentage of total delay, forcing the timing optimization into later stages of the design. A number of solutions have been dispatched at the problem, including physical synthesis, iterative refinement, improved timing optimization in place-and-route and synthesis, and floorplanning.

While each of these approaches has its merits, floorplanning has acquired a bit of a bad name over the years. The reason is that floorplanning generally requires skill. A primitive floorplanner in the hands of an inexperienced designer is a sure-fire recipe for more problems than you can solve. PlanAhead, however, seems not to suffer from that problem. Its user interface is intuitive, and you’re likely to begin using it as an analysis tool rather than a floorplanner. Of course, once you’re able to locate and understand the problem areas of your design, you won’t be able to resist clustering a few parts of your design together to get better timing results, and the first thing you know – you’re off and floorplanning.

Xilinx claims that they’ve seen an average of 24% faster performance with PlanAhead 8.1 compared to ISE alone, and that “tough, multi-clock” designs see over 50% better performance. Like any process that involves skill, your results will vary according to yours. PlanAhead helps you get the information you need to make the right decisions, however, so the rest should be well within your grasp.

When properly used, PlanAhead should help break the iterative timing-closure loop between synthesis and place-and-route. This not only makes meeting timing simpler, it makes schedules more predictable. Almost nothing is worse than trying to schedule timing closure on a project when the design simply won’t converge. Running an iterative loop and hoping for a random, successful result isn’t anybody’s idea of a fun time in engineering.

Besides locking in timing closure, however, PlanAhead has other interesting applications. If your design is done by a team, and if every engineer on your team doesn’t work at exactly the same speed, you’ll often end up in a situation where one part of the design is ready for place-and-route while another is still back in RTL functional debug. With the aid of a planning tool like PlanAhead, you can partition separate areas of the FPGA for each part of the design, and each engineer can work on debug, timing closure, and integration of his or her part separately. Once all the parts are ready, you can integrate the entire design, and, hopefully, you’ll end up debugging only the interfaces. Best of all, if a change or update is required to one section of the design, all the other sections should go on working correctly instead of being subject to the whimsical moods of re-placement, the timing closure groundhog, and renewed timing problems.

Although we’re hesitant to mention it, PlanAhead 8.1 also addresses another emerging area of FPGA design – partial reconfiguration. Partial reconfiguration is today’s extreme sport of FPGA design, daring black-belt designers to test their mettle against daunting odds to get part of an FPGA to reconfigure while the rest hums along with the original programming. Partial reconfiguration is a potential solution to a plethora of problems, but it poses enough severe challenges on its own that it hasn’t yet proven itself a practical panacea for anything. With PlanAhead 8.1, however, the challenge got just a little more manageable, as the floorplanning capabilities in PlanAhead allow a region to be defined and protected for partial reconfiguration. As advanced applications like software-defined radio take increasing advantage of the reprogrammable nature of FPGAs, partial reconfiguration will migrate from daredevil designer stunt to practical problem solution with the help of simplifying tools like PlanAhead.

With the 8.1 release, PlanAhead has an increased level of integration with the rest of the Xilinx toolset. One of those integration niceties is a capability called “ExploreAhead” that runs, manages, and monitors multiple ISE runs (even on multiple processors) and gathers and compares the results. This allows us to batch up our place-and-route runs and to quickly compare and analyze the results at the end, after a good night’s (or coffee break’s, depending on your design size) worth of cpu time. PlanAhead is also one of the few places where you can get good schematic-level views of the key portions of your design. Schematic views can sometimes be an invaluable aid in understanding and debugging timing problems.

It’s refreshing to see a company continue to press ahead and even accelerate development of an acquired product after an acquisition. Too often, the announcements are made, and then the startup company’s products disappear into the larger company’s lab, never to be heard from again. PlanAhead brings an important set of capabilities to the table for FPGA design, and its continued development is a win for the design community. Even the groundhog is happy.

Leave a Reply

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...