Price, Performance, and Power – the three Ps of Moore’s Law — have fueled four decades of technological fury. Each new process node brought us more gates per square meter of silicon, reducing price. Each shrink of the gate also brought us faster toggle rates, giving higher performance, and each narrowing also gave us the opportunity to operate at lower supply voltages, giving less dynamic power consumption. It seemed as if everything would improve exponentially forever.

Of course, nothing is free. There has always been another exponential curve at work as well – that of increasing costs. Each generation has cost geometrically more than the last, and the number of companies with the wherewithal to make the next node has withered with each wave. Smaller companies with fewer resources began to piggyback on the development efforts of larger companies, and a hierarchy of specialization emerged. Most systems companies long ago got out of the fabrication business and consolidated their efforts by going “fabless,” leveraging one of a few large fabrication facilities that quickly garnered much of the world’s semiconductor manufacturing business.

During the same period, many systems companies also relieved themselves of the burden of developing basic IC architectures, preferring instead to piggyback on a number of fabless semiconductor specialists (like ASIC and FPGA vendors) who created general-purpose architectures and tool flows to allow rapid development of systems from basic building blocks. Today, the accepted order of things is for systems companies to deal with fabless semiconductor companies (and sometimes EDA companies). Those companies then deal with the semiconductor fabs, EDA tool suppliers, and IP companies to put together the silicon platforms that they offer to their system-designing customers.

FPGA companies like Xilinx, Altera, Actel, Lattice, and QuickLogic have gained momentum over the past two decades by moving ahead in line at the semiconductor fabs. In the beginning, they were at the back of the pack, waiting for memory and ASIC companies to come up to speed on a new process node before they took their turn. Today, however, the leading FPGA vendors tend to be first, shaking out the each new process node before the rest of the industry comes along.

Being first in line has its benefits. FPGAs tend to have at least a one-process-node advantage over many competitive architectures. That means that their inherent architectural inefficiencies (lower logic density and higher power consumption) are masked by the improved characteristics of a more advanced process. This “one node ahead” effect has leveled the playing field for FPGAs against many other technologies over the past decade.

Being first in line also has disadvantages. By being the first to blaze the trail on each new process geometry, FPGA companies were left to develop a lot of first-time technology themselves. Problems like leakage current, exploding interconnect delay, deep sub-micron feature fuzziness, and ground-level single-event upsets haven’t been fully worked out when the FPGA development engineers arrive. They are left with the expensive and expansive process of experimenting with architectures and recipes to find one combination that will strike the right balance, overcoming the challenges of the new, smaller process geometry and still delivering the three Ps of progress that we’ve come to expect with a new process node.

This week, Xilinx gave a glimpse into their 65nm progress by announcing fabrication agreements with both UMC and Toshiba. Part of Xilinx’s risk mitigation strategy for 65nm involves leveraging multiple fab partners. While it is more complicated and expensive to work with two fabs, you also don’t have all your eggs in one basked if you hit a snag, or if one fab is having process problems. It’s like betting on two horses in the same race. You spend more on your wager, but you’ve got double the chances of picking the winner.

Xilinx claims that they plan to maintain their two-tiered architecture approach with 65nm, optimizing the high-end devices for raw performance and capability while constraining power and cost, and optimizing the low-cost devices for cost, size, and power while maintaining “just enough performance” for key target applications.

Unlike 90nm, however, Xilinx plans to return to their traditional practice of launching their flagship Virtex-class family first on 65nm, then following with their cost-optimized Spartan-class series. In the previous generation, Xilinx first introduced Spartan-3 (their low-cost family) and began ramping that family to volume while still working toward the introduction of their high-end Virtex-4 family. It is possible that the 90nm decision was based partly on competitive pressures – Altera was being highly successful with their cost-optimized Cyclone (130nm) family against Xilinx’s Spartan series, and Xilinx may have felt they needed the 90nm boost to regain competitiveness in the hotly contested high-volume segment.

Xilinx is also apparently sticking to their Virtex-4-style column-based architecture, producing a variety of device types with different mixes of hard-IP targeting different end-application styles. With Virtex-4, Xilinx was able to make specific versions of the family optimized for DSP and for embedded processing (SX and FX), leaving the “standard” LX product with more room for random logic and less power and area (and cost) overhead from hard-IP. While Xilinx isn’t yet being specific, we may see even more variants in the upcoming 65nm line.

Xilinx also pulled back the curtain a bit to reveal some of the new challenges at 65nm. They say that techniques and tools such as design for manufacturing (DFM), which were helpful at 90nm, have become mandatory at 65nm. Advanced capabilities such as resolution enhancement technology (RET), where features are pre-distorted on the mask in order to make them render as desired on the wafer, are necessary to get yield at 65nm.

Since core voltages are stepping down even farther, the design/process window is shrinking even more, making it difficult to tune the process to get the zeros and ones right. At the same time, process variability is increasing, now with significant variations seen even across a single die instead of just from chip to chip, wafer to wafer, or lot to lot. With more variation in the process and less tolerance to variation in the design, the magic balance point between design and manufacturing is smaller than ever. Xilinx says that success in this new, more challenging environment is predicated on a close working partnership with the fab up front, before design begins, instead of during the process and at the end as in past generations.

Just as interesting as what 65nm means to Xilinx is what it means to the rest of the industry. While Xilinx and their partners claim to have actual fabrics and PLD structures already done at 65nm, only one FPGA competitor (Altera) is shipping, or has even announced 90nm products. This means that sometime in the next two years, Xilinx (and Altera) could have more than a two-process advantage over many of the smaller competitors. That’s a differential that makes it impossible to compete head-to-head on silicon. Any successful niche competitor will have to offer significant differentiation elsewhere to overcome the high-ground position on Moore’s Law.

Already, we see competitors like Actel and QuickLogic focusing on other technology differentiators – Flash- and antifuse-based fabrics, application-specific IP, partnerships with leading processor core providers, and marketing efforts targeting specific, high-growth segments still give them more than a fighting chance to win specific, high-value sockets with their devices.

Arch-rival Altera is almost certainly already engaged in 65nm work of their own, with the traditional battle of the press release providing a public façade for the real competition going on behind the scenes. Also, while the race to 65 is clearly a major and important ingredient in competitive success, the business battle between Xilinx and Altera will almost certainly be influenced far more by other factors such as the quality and diversity of IP and tools offered, the effectiveness of marketing strategies in targeting high-growth applications, and execution excellence in production volume manufacturing.

With this early glimpse into what is happening now, we can probably expect to see more specific architecture and product announcements on 65nm FPGAs sometime in 2006. If this node follows the path of previous generations, that means that the first volume production would happen sometime in 2007, and the public will be buying millions of electronic widgets and whirlygigs with 65nm FPGAs in them just in time for the 2008 gift-giving season.